Datasheet

1-Wire Bus System
The 1-Wire bus system uses a single bus master to con-
trol one or more slave devices. The DS18B20 is always a
slave. When there is only one slave on the bus, the sys-
tem is referred to as a “single-drop” system; the system is
“multidrop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant
bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is
broken down into three topics: hardware configuration,
transaction sequence, and 1-Wire signaling (signal types
and timing).
Hardware Conguration
The 1-Wire bus has by definition only a single data line.
Each device (master or slave) interfaces to the data line
via an open-drain or 3-state port. This allows each device
to “release” the data line when the device is not transmit-
ting data so the bus is available for use by another device.
The 1-Wire port of the DS18B20 (the DQ pin) is open
drain with an internal circuit equivalent to that shown in
Figure 12.
The 1-Wire bus requires an external pullup resistor of
approximately 5kΩ; thus, the idle state for the 1-Wire
bus is high. If for any reason a transaction needs to be
suspended, the bus MUST be left in the idle state if the
transaction is to resume. Infinite recovery time can occur
between bits so long as the 1-Wire bus is in the inactive
(high) state during the recovery period. If the bus is held
low for more than 480µs, all components on the bus will
be reset.
Transaction Sequence
The transaction sequence for accessing the DS18B20 is
as follows:
Step 1. Initialization
Step 2. ROM Command (followed by any required data
exchange)
Step 3. DS18B20 Function Command (followed by any
required data exchange)
It is very important to follow this sequence every time the
DS18B20 is accessed, as the DS18B20 will not respond
if any steps in the sequence are missing or out of order.
Exceptions to this rule are the Search ROM [F0h] and
Alarm Search [ECh] commands. After issuing either of
these ROM commands, the master must return to Step 1
in the sequence.
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that slave devices
(such as the DS18B20) are on the bus and are ready
to operate. Timing for the reset and presence pulses is
detailed in the 1-Wire Signaling section.
ROM Commands
After the bus master has detected a presence pulse, it
can issue a ROM command. These commands operate
on the unique 64-bit ROM codes of each slave device
and allow the master to single out a specific device if
many are present on the 1-Wire bus. These commands
also allow the master to determine how many and what
types of devices are present on the bus or if any device
has experienced an alarm condition. There are five ROM
commands, and each command is 8 bits long. The master
device must issue an appropriate ROM command before
issuing a DS18B20 function command. A flowchart for
operation of the ROM commands is shown in Figure 13.
Search Rom [F0h]
When a system is initially powered up, the master must
identify the ROM codes of all slave devices on the bus,
which allows the master to determine the number of
slaves and their device types. The master learns the
ROM codes through a process of elimination that requires
the master to perform a Search ROM cycle (i.e., Search
ROM command followed by data exchange) as many
times as necessary to identify all of the slave devices.
Figure 12. Hardware Configuration
DQ
V
PU
4.7kΩ
DS18B20
1-WIRE PORT
Rx
Tx
100Ω
MOSFET
5µA
TYP
1-WIRE BUS
Rx
Tx
R x = RECEIVE
Tx = TRANSMIT
DS18B20 Programmable Resolution
1-Wire Digital Thermometer
www.maximintegrated.com
Maxim Integrated │ 10