Datasheet

ams Datasheet Page 19
[v1-08] 2020-Jun-29 Document Feedback
TMF8701 − Register Description
Figure 24:
ENABLE Register
Figure 25:
INT_STATUS Register
0xe0: ENABLE
Field Name Reset Type Description
7cpu_reset 0 RW_SC
Write a '1' here to reset CPU. This generates global
reset, fully resetting CPU and all CPU registers. The bit
resets itself, no need to explicitly clear it.
6 cpu_ready 0 RO
CPU is ready to handle I²C - if this bit is zero, then only
the registers 0xe0 and above are usable, the memory
mapped I²C space is not used.
Bit gets set only explicitly by software, therefore a
functional and running firmware is necessary for this
bit to work.
0 pon 1 R_PUSH
1 = Activate oscillator
0 = Ask cpu to go to standby
Activating the oscillator is implemented in hardware.
Whenever this register is '0' and a '1' is being written,
the oscillator is being started and CPU receives a
PON1 interrupt. It is implemented in the bootloader
to execute a reset at this point, but the application
goes to an IDLE state.
De-activating the oscillator is a software assisted
process. It is important that the CPU powers down all
modules properly before turning off the oscillator,
therefore this is implemented in firmware. So writing a
'0' to this register will trigger an internal CPU interrupt.
The firmware, after powering down everything, sets
the device into standby state.
0xe1: INT_STATUS
Field Name Reset Type Description
1 int2 0 R_PUSH1
Raw histogram available interrupt for App0; asserted
when a raw histogram can be retrieved from I²C.
int2 status. If bis is asserted, and int2_enab is asserted as
well, then the INT pin will be pulled low. Writing a '1' here
will clear int1 condition.
0 int1 0 R_PUSH1
Object detection interrupt for App0; asserted when a
result from object detection is available
int1 status. If bis is asserted, and int1_enab is asserted as
well, then the INT pin will be pulled low. Writing a '1' here
will clear int1 condition.