Datasheet

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Page 10 ams Datasheet

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TMF8701 − Detailed Description

I²C Protocol

The TMF8701 is controlled by an I²C bus, one interrupt pin and

two GPIO pins.

The device uses I²C serial communication protocol for

communication. The device supports 7-bit chip addressing and

standard, fast mode and fast mode plus modes. Read and Write

transactions comply with the standard set by Philips (now NXP).

For a complete description of the I²C protocol, please review

the NXP I²C design specification.

Internal to the device, an 8-bit buffer stores the register address

location of the byte to read or write. This buffer auto-increments

upon each byte transfer and is retained between transaction

events (i.e. valid even after the master issues a STOP and the I²C

bus is released). During consecutive Read transactions, the

future/repeated I²C Read transaction may omit the memory

address byte normally following the chip address byte; the

buffer retains the last register address +1.

A Write transaction consists of a START, CHIP-ADDRESSWRITE,

each byte (9

clock pulse) the slave places an

ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus.

If NACK is transmitted by the slave, the master may issue a STOP.

A Read transaction consists of a START, CHIP-ADDRESSWRITE,

BYTE(S), and STOP. Following all but the final byte the master

places an ACK on the bus (9TH clock pulse). Termination of the

Read transaction is indicated by a NACK being placed on the

bus by the master, followed by STOP.

Detailed Description