Datasheet
Table Of Contents
- 1. Specification
- 2. Absolute maximum ratings
- 3. Block diagram
- 4. Functional description
- 5. Register Description
- 6. Digital interfaces
- 7. Pin-out and connection diagram
- 8. Package
- 10. Legal disclaimer
- 11. Document history and modification
Datasheet
BMM150 Geomagnetic Sensor
Page 35
BST-BMM150-DS001-01 | Revision 1.0 | April 2013 Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are subject to change without notice.
Figure 10: 4-wire basic SPI read sequence (mode “11”)
The data bits are used as follows:
Bit0: Read/Write bit. When 0, the data SDI is written into the chip. When 1, the data SDO from
the chip is read.
Bit1-7: Address AD(6:0).
Bit8-15: when in write mode, these are the data SDI, which will be written into the address.
When in read mode, these are the data SDO, which are read from the address.
Multiple read operations are possible by keeping CSB low and continuing the data transfer.
Only the first register address has to be written. Addresses are automatically incremented after
each read access as long as CSB stays active low.
The principle of multiple read is shown in Figure 11:
Figure 11: SPI multiple read
In SPI 3-wire configuration CSB (chip select low active), SCK (serial clock), and SDI (serial
data input and output) pins are used. The communication starts when the CSB is pulled low by
the SPI master and stops when CSB is pulled high. SCK is also controlled by SPI master. SDI is
driven (when used as input of the device) at the falling edge of SCK and should be captured
(when used as the output of the device) at the rising edge of SCK.
The protocol as such is the same in 3-wire configuration as it is in 4-wire configuration. The
basic operation waveform (read or write access) for 3-wire configuration is depicted in Figure
12:
Start
RW Stop
1 0 0 0 0 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X
Register adress (02h)
CSB
=
0
CSB
=
1
Data byte
Data byte
Data register - adress 03h
Data register - adress 04h
Control byte
Data byte
Data register - adress 02h
CS
B
SC
K
SD
I
R/W
AD
6
AD
5
A
D
4
A
D
3
A
D
2
AD
1
AD
0
SD
O
DO
5
DO
4
DO
3
DO
2
DO
1
DO
0
DO
7
DO
6
tr
i
-
stat
e