Data Sheet

SD2405ALPI IIC 串行接口的实时时钟IC
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3) Here, the clock accuracy at room temperature varies along with the variation of the
characteristic of crystal oscillator.
4) The influence of stray capacitance on circuit board
These factors will cause large errors
Using the time trimming circuit gain or lose of clock may be adjusted with high
precision by changing clock pulses for one second every 20 seconds.
F6 to F0:
The time trimming circuit adjust one second count based on this register readings
when second digit is 0020or 40 seconds. Normally, counting up to seconds
is made once per 32,768 of clock pulse (or 32,000 when 32.000KHz crystal is
used) generated by the oscillator. Setting data to this register activates the time
trimming circuit.
Register counts will be incremented as ((F5, F4, F3, F2, F1, F0)-1) x2 when F6 is
set to0”.
Register counts will be decremented as ((/F5, /F4, /F3, /F2, /F1, /F0) +1) x2 when
F6 is set to “1”.
Counts will not change when (F6, F5, F4, F3, F2, F1, F0) are set to (*, 0, 0, 0, 0, 0, *).
For example, when 32.768KHz crystal is used.
When (F6, F5, F4, F3, F2, F1, F0) are set to (0,1, 0, 1, 0, 0, 1), counts will change
as:
32768+29-1*2=32824
(clock will be delayed) when second digit is 00,
20, or 40.
When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain
32,768 without changing when second digit is 00, 20, or 40.
When (F6, F5, F4, F3, F2, F1, F0) are set to (1, 1, 1, 1, 1, 1, 0), counts will
change as: 32768-1+1*2=32764 (clock will be advanced) when second
digit is 00, 20, or 40.
Adding 2 clock pulses every 20 seconds:
2/32768*20=3.051ppm
(or 3.125ppm
when 32.000KHZcrystal is used), delays the clock by approx. 3ppm.
Likewise, decrementing 2 clock pulses advances the clock by 3ppm. Thus
the clock may be adjusted to the precision of±1.5ppm.
Note: that the time trimming function only adjusts clock timing and oscillation
frequency but 32.768KHz clock output is not adjusted
Computational method of time trimming register value
1. When oscillation frequency
*1
> target frequency
*2
clock gain