Data Sheet

iEthernet

W5200

wait for at least 150ms after high de-assert in order for

PLL logic to be stable. Refer to RESET timing of “7

Electrical Specification”

CSn I 41 SPI SLAVE SELECT ( Active LOW )

This pin is used to SPI Slave Select signal Pin when using

SPI interface.

(*)CHIP SELECT ( Active LOW )

Chip Select is for MCU to access to internal registers or

memory when using indirect interface.

INTn O 40 INTERRUPT (Active LOW )

This pin indicates that W5200 requires MCU attention

after socket connecting, disconnecting, data receiving

timeout, and WOL (Wake on LAN). The interrupt is

cleared by writing IR(Interrupt Register) or Sn_IR (Socket

n Interrupt Register). All interrupts are maskable. This

pin is active low.

SCLK/RDn I 42 SPI CLOCK

This pin is used to SPI Clock signal Pin when using SPI

interface.

(*)READ ENABLE ( Active LOW )

Strobe from MCU to read an internal register/memory

selected by A[1:0] when using indirect interface.

MOSI/WRn

I 43 SPI MASTER OUT SLAVE IN

This pin is used to SPI MOSI signal pin when using SPI

interface.

(*)WRITE ENABLE ( Active LOW )

Strobe from MCU to write an internal register/memory

selected by A[1:0] when using indirect interface. Data is

latched into the W5200 on the rising edge of this input.

MISO O 44 SPI MASTER IN SLAVE OUT

This pin is used to SPI MISO signal pin.

PWDN I 45 POWER DOWN ( Active HIGH )

This pin is used to power down pin.

Low : Normal Mode Enable

High : Power Down Mode Enable

SPIEN I 6 (*)SPI ENABLE ( Active HIGH )

This pin selects Enable/disable of the SPI Mode.

Low = SPI Mode Disable

High = SPI Mode Enable