Data Sheet

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81
iEthernet
W5200
7.4.3 SPI Timing
Figure 24 SPI Timing
5
Theoretical Guaranteed Speed
Even though theoretical design speed is 80MHz, the signal in the high speed may be distorted because of
the circuit crosstalk and the length of the signal line. The minimum guaranteed speed of the SCLK is
33.3 MHz which was tested and measured with the stable waveform.
6
2.1ns is when pn loaded with 30pF. The time is shorter with lower capacitance.
Symbol Description Min Max Units
F
SCK
SCK Clock Frequency 80/33.3
5
MHz
T
WH
SCK High Time 6 ns
T
WL
SCK Low Time 6 ns
T
CS
CSn High Time 5 ns
T
CSS
CSn Setup Time 5 - ns
T
CSH
CSn Hold Time 5 ns
T
DS
Data In Setup Time 3 ns
T
DH
Data In Hold Time 3 ns
T
OV
Output Valid Time 5 ns
T
OH
Output Hold Time 0 ns
T
CHZ
CSn High to Output Hi-Z 2.1
6
ns