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41
iEthernet
W5200
physical address(hereafter, we'll call get_start_address).
Sn_RX_WR (Socket n RX Write Pointer Register)[R/W][(0x402A + 0x0n00) – (0x402B +
0x0n00)][0x0000]
This register offers the location information to write the receive data. When reading this
register, the user should read upper bytes (0x402A, 0x412A, 0x422A, 0x432A, 0x442A, 0x452A,
0x462A, 0x472A) first and lower bytes (0x402B, 0x412B, 0x422B, 0x432B, 0x442B, 0x452B,
0x462B, 0x472B) later to get the correct value.
Ex) In case of 2048(0x0800) in S0_RX_WR,
0x402A 0x402B
0x08 0x00
Sn_IMR (Socket n Interrupt Mask Register)[R/W][0x402C+0x0n00][0xFF]
It configures the interrupt of Socket n so as to notify to the host. Interrupt mask bit of
Sn_IMR corresponds to interrupt bit of Sn_IR. If interrupt occurs in any SOCKET and the bit is
set as ‘1’, its corresponding bit of Sn_IR is set as ‘1’. When the bits of Sn_IMR and Sn_IR are
‘1’, IR(n) becomes ‘1’. At this time, if IMR(n) is ‘1’, the interrupt is issued to the host. (‘INTn’
signal is asserted low)
7 6 5 4 3 2 1 0
PRECV
PFAIL
PNEXT
SEND_OK
TIMEOUT
RECV DISCON CON
Bit Symbol Description
7
PRECV Sn_IR(PRECV) Interrupt Mask
Valid only in case of ‘SOCKET = 0’ & ‘S0_MR(P3:P0) = S0_MR_PPPoE’
6
PFAIL Sn_IR(PFAIL) Interrupt Mask
Valid only in case of ‘SOCKET = 0’ & ‘S0_MR(P3:P0) = S0_MR_PPPoE’
5
PNEXT Sn_IR(PNEXT) Interrupt Mask
Valid only in case of ‘SOCKET = 0’ & ‘S0_MR(P3:P0) = S0_MR_PPPoE’
4 SENDOK Sn_IR(SENDOK) Interrupt Mask
3 TIMEOUT Sn_IR(TIMEOUT) Interrupt Mask
2 RECV Sn_IR(RECV) Interrupt Mask
1 DISCON Sn_IR(DISCON) Interrupt Mask
0 CON Sn_IR(CON) Interrupt Mask