Datasheet

ST7735
V1.7 23 2009-12-04
8.2 Serial interface characteristics (3-line serial)
CSX
V
IH
V
IL
T
CHW
T
CSH
T
OH
T
CSS
SCL
SDA
SDA
(DOUT)
T
SCC
T
SCYCW
/T
SCYCR
T
ACC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
T
SDS
T
SDH
T
SHW
/T
SHR
T
SLW
/T
SLR
Fig. 8.2.1 3-line serial interface timing
Signal Symbol Parameter Min Max Unit Description
TCSS Chip select setup time (write) 15 ns
TCSH Chip select hold time (write) 15 ns
TCSS Chip select setup time (read) 60 ns
TSCC Chip select hold time (read) 65 ns
CSX
TCHW Chip select “H” pulse width 40 ns
TSCYCW Serial clock cycle (Write) 66 ns
TSHW SCL “H” pulse width (Write) 30 ns
TSLW SCL “L” pulse width (Write) 30 ns
TSCYCR Serial clock cycle (Read) 150 ns
TSHR SCL “H” pulse width (Read) 60 ns
SCL
TSLR SCL “L” pulse width (Read) 60 ns
TSDS Data setup time 10 ns
TSDH Data hold time 10 ns
TACC Access time 10 50 ns
SDA
(DIN)
(DOUT)
TOH Output disable time 50 ns
For maximum CL=30pF
For minimum CL=8pF
Table 8.2.1 3-line Serial Interface Characteristics
Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.