Datasheet

ST7735
V1.7 126 2009-12-04
10.2.5 DISSET5 (B6h): Display Function set 5
B6H DISSET (Display Function set 5)
Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
DISSET5 0 ↑ 1 - 1 0 1 1 0 1 1 0 (B6h)
1
st
parameter 1 ↑ 1 - 0 0 NO1 NO0 SDT1 SDT0 EQ1 EQ0
2
nd
parameter 1 ↑ 1 - 0 0 0 0 PTG1 PTG0 PT1 PT0
Description
1st parameter: Set output waveform relation.
-NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0]
Amount of non-overlap of the gate
output
Refer the Internal oscillator
00 00h 1 clock cycle
01 01h 2 clock cycle
10 02h 4 clock cycle
11 03h 6 clock cycle
-SDT[1:0]: Set delay amount from gate signal rising edge of the source output .
SDT[1:0]
Delay amount form gate signal rising
edge of the source output
Refer the Internal oscillator
00 00h 0 clock cycle
01 01h 1 clock cycle
10 02h 2 clock cycle
11 03h 3 clock cycle
- EQ[1:0]: Set the Equalizing period
EQ[1:0] Equalizing period
Refer the Internal oscillator
00 00h No EQ
01 01h 3 clock cycle
10 02h 5 clock cycle
11 03h 7 clock cycle
-2nd parameter: Set the output waveform in non-display area.
-PTG[1:0]: Determine gate output in a non-display area in the partial mode
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
PTG[1:0] Gate output in a non-display area
00 00h Normal scan
01 01h Fix on VGL
10 02h Fix on VGL
11 03h Fix on VGL
PT[1:0] Source output on non-display area VCOM output on non-display area
Positive Negative Positive Negative
00 00h V63 V0 VCOML VCOMH
01 01h V0 V63 VCOML VCOMH
10 02h AGND AGND AGND AGND
11 03h Hi-z Hi-z AGND AGND