Data Sheet

NUC123
May 3, 2017 Page 64 of 99 Rev.2.04
NUC123 SERIES DATASHEET
USB Device Controller (USB) 6.16
6.16.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/
Isochronous transfer types.
In this device controller, there are two main interfaces: APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it.
There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (BUFSEGx).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data
sequential synchronization, endpoint state control, current start address, transaction status, and
data buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up event, device
plug-in or plug-out event, USB events, such as IN ACK, OUT ACK, and BUS events, such as
suspend and resume, etc. Any event will cause an interrupt, and user just needs to check the
related event flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of
interrupt occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB
controller will force the output of USB_D+ and USB_D- to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate this USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus
Specification Revision 1.1.
6.16.2 Features
 Compliant with USB 2.0 Full-Speed specification
 Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB and
BUS)
 Supports Control/Bulk/Interrupt/Isochronous transfer types
 Supports suspend function when no bus activity existing for 3 ms
 Provides 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and
maximum 512 bytes buffer size
 Provides remote wake-up capability