Data Sheet

NUC123
May 3, 2017 Page 54 of 99 Rev.2.04
NUC123 SERIES DATASHEET
PDMA Controller (PDMA) 6.6
6.6.1 Overview
The NuMicro
®
NUC123 contains a six-channel peripheral direct memory access (PDMA)
controller and a cyclic redundancy check (CRC) generator.
The PDMA can transfer data to and from memory or transfer data to and from APB devices. For
PDMA channel (PDMA CH0~CH5), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. The CPU can recognize the completion of a PDMA
operation by software polling or when it receives an internal PDMA interrupt. The PDMA controller
can increase source or destination address or fixed them as well.
The PDMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode
and PDMA transfer mode.
6.6.2 Features
 Supports six PDMA channels and one CRC channel; each PDMA channel can support a
unidirectional transfer
 AMBA AHB master/slave interface compatible, for data transfer and register read/write
 Hardware round robin priority scheme. PDMA channel 0 has the highest priority
 PDMA
– Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
– Supports word/half-word/byte transfer data width from/to peripheral
– Supports address direction: increment, fixed
– Supports software, SPI, UART, ADC, PWM and I
2
S request
 Cyclic Redundancy Check (CRC)
– Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
 CRC-CCITT: X
16
+ X
12
+ X
5
+ 1
 CRC-8: X
8
+ X
2
+ X + 1
 CRC-16: X
16
+ X
15
+ X
2
+ 1
 CRC-32: X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+ X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X + 1
– Programmable seed value
– Supports programmable order reverse setting for input data and CRC checksum
– Supports programmable 1’s complement setting for input data and CRC checksum.
– Supports CPU PIO mode or PDMA transfer mode
– Supports 8/16/32-bit of data width in CPU PIO mode
 8-bit write mode: 1-AHB clock cycle operation
 16-bit write mode: 2-AHB clock cycle operation
 32-bit write mode: 4-AHB clock cycle operation
– Supports byte alignment transfer length in CRC PDMA mode