Data Sheet

NUC123
May 3, 2017 Page 50 of 99 Rev.2.04
NUC123 SERIES DATASHEET
6.3.2 System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-11.
111
011
010
PLLFOUT
HXT (4~24 MHz)
LIRC (10 KHz)
HIRC (22.1184 MHz)
000
1/(HCLK_N+1)
PCLK1/(APBDIV+1)
001
1/2
CPUCLK
HCLK
CPU in Power Down Mode
HCLK_S (CLKSEL0[2:0])
CPU
AHB
APB
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6-11 System Clock Block Diagram
The clock source of SysTick in Cortex
®
-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-12.
111
011
010
000
1/2
1/2
1/2
HCLK
STCLK_S (CLKSEL0[5:3])
STCLK
HIRC (22.1184 MHz)
HXT (4~24 MHz)
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on
and stable.
Figure 6-12 SysTick Clock Control Block Diagram
6.3.3 Peripherals Clock
The peripherals clock had different clock source switch setting depending on different peripherals.
Please refer to the CLKSEL1 and CLKSEL2 register description in TRM.
6.3.4 Power-down Mode Clock
When chip enters into Power-down mode, system clocks, some clock sources, and some
peripheral clocks will be disabled. Some clock sources and peripherals clock are still active in
Power-down mode.
The clocks kept active are listed below:
 Clock Generator
– Internal 10 kHz low speed oscillator clock