Data Sheet

NUC123
May 3, 2017 Page 36 of 99 Rev.2.04
NUC123 SERIES DATASHEET
6.2.3 Power modes and Wake-up sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LIRC.
SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction.
CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD
and GPIO
Available Clocks
All
All except CPU clock
LIRC
After Wake-up
N/A
CPU back to normal mode
CPU back to normal mode
Table 6-2 Power Mode Difference Table
Normal Mode
CPU Clock ON
HXT, HIRC, LIRC, HCLK, PCLK ON
Flash ON
Power-down Mode
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
Flash Halt
System reset released
CPU executes WFI Interrupts occur
Idle Mode
CPU Clock OFF
HXT, HIRC, LIRC, HCLK, PCLK ON
Flash Halt
1. SLEEPDEEP(SCR[2]) = 1
2. PWR_DOWN_EN (PWRCON[7]) = 1
PD_WAIT_CPU (PWRCON[8]) = 1
3. CPU executes WFI
Wake-up events
occur
LIRC ON
Figure 6-7 Power Mode State Machine