Data Sheet

NUC123
May 3, 2017 Page 35 of 99 Rev.2.04
NUC123 SERIES DATASHEET
AV
DD
V
BODL
BODOUT
BODRSTEN
Brown-out
Reset
T
1
(< de-glitch time)
T
2
(= de-glitch time)
T
3
(= de-glitch time)
Hysteresis
V
BODH
Figure 6-6 Brown-Out Detector Waveform
Watch Dog Timer Reset 6.2.2.5
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watch dog timer (WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watch dog time-out. User may decide to enable system reset during watch dog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watch dog time-out to indicate the previous reset is a
watch dog reset and handle the failure of MCU after watch dog time-out reset by checking
RSTS_WDT (RSTSRC[2]).
CPU Reset, CHIP Reset and MCU Reset 6.2.2.6
The CPU Reset means only Cortex
®
-M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPU Reset CPU_RST (IPRSTC1[1]) to 1 to assert the
CPU Reset signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS
(ISPCON[1]) bit is automatically reloaded from CONFIG0 setting. User can set the CHIP Reset
CHIP_RST (IPRSTC1[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS (ISPCON[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the MCU Reset SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.