Data Sheet

NUC123
May 3, 2017 Page 33 of 99 Rev.2.04
NUC123 SERIES DATASHEET
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 V
DD
and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will
be set to 1 if the previous reset source is nRESET reset.
SS
nRESET
0.2 V
DD
0.7 V
DD
nRESET Reset
SS
36 us
36 us
Figure 6-3 shows the nRESET reset waveform.
SS
nRESET
0.2 V
DD
0.7 V
DD
nRESET Reset
SS
36 us
36 us
Figure 6-3 nRESET Reset Waveform
Power-On Reset (POR) 6.2.2.2
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be
set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared
by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset.
V
DD
V
POR
Power On
Reset
0.1V