Data Sheet

NUC123
May 3, 2017 Page 28 of 99 Rev.2.04
NUC123 SERIES DATASHEET
6 FUNCTIONAL DESCRIPTION
ARM
®
Cortex
®
-M0 Core 6.1
The Cortex
®
-M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA
AHB-Lite interface and includes an NVIC component. The processor has optional hardware
debug functionality, can execute Thumb code, and is compatible with other Cortex
®
-M profile
processors. The profile supports two modes -Thread mode and Handler mode. Handler mode is
entered as a result of an exception. An exception return can only be issued in Handler mode.
Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure
6-1 shows the functional controller of processor.
Cortex-M0
Processor
Core
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Debugger
interface
Bus Matrix
Debug
Access
Port
(DAP)
Debug
Cortex-M0 processor
Cortex-M0 components
Wakeup
Interrupt
Controller
(WIC)
Interrupts
Serial Wire or
JTAG debug port
AHB-Lite
interface
Figure 6-1 Functional Controller Diagram
The implemented device provides:
 A low gate count processor:
– ARMv6-M Thumb® instruction set
– Thumb-2 technology
– ARMv6-M compliant 24-bit SysTick timer
– A 32-bit hardware multiplier
– System interface supporting little-endian data accesses
– Ability to have deterministic, fixed-latency, interrupt handling
– Load/store-multiples and multicycle-multiplies abandoned and restarted to
facilitate rapid interrupt handling
– C Application Binary Interface compliant exception model, which is the ARMv6-
M, C Application Binary Interface (C-ABI) compliant exception model that
enables the use of pure C functions as interrupt handlers
– Low power sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
 NVIC :