Data Sheet

NUC123
May 3, 2017 Page 10 of 99 Rev.2.04
NUC123 SERIES DATASHEET
– 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog timer time-out
– Interrupt on windowed-watchdog timer time-out
– Reset on windowed-watchdog timer time-out or reload in an unexpected time window
 PWM/Capture
– Up to two built-in 16-bit PWM generators provided with four PWM outputs or two
complementary paired PWM outputs
– Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-zone generator for complementary paired PWM
– Up to four 16-bit digital Capture timers (shared with PWM timers) provided with four
rising/falling capture inputs
– Supports Capture interrupt
 UART
– Up to two UART controllers
– UART ports with flow control (TXD, RXD, CTS and RTS)
– UART0/1 with 16-byte FIFO for standard device
– Support IrDA (SIR) function
– Supports RS-485 9-bit mode and direction control.
– Programmable baud-rate generator up to 1/16 system clock
– Supports PDMA mode
 SPI
– Up to three sets of SPI controllers
– Supports SPI master/Slave mode
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 8 to 32 bits
– MSB or LSB first data transfer
– Up to two slave/device select lines in Master mode
– Supports Byte Suspend mode in 16/24/32-bit transmission
– Supports PDMA transfer
 I
2
C
– Up to two sets of I
2
C devices
– Master/Slave mode
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master)
– Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
– Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
– Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
– Programmable clocks allowing versatile rate control
– Supports multiple address recognition (four slave address with mask option)
– Supports wake-up by address recognition (for 1st slave address only)
 I
2
S
– Interface with external audio CODEC
– Operated as either master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports Mono and stereo audio data
– Supports I
2
S and MSB justified data format
– Two 8 word FIFO data buffers are provided, one for transmitting and the other for
receiving