Data Sheet

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NUC123

May 3, 2017 Page 1 of 99 Rev.2.04

NUC123 SERIES DATASHEET

ARM

Cortex

-M0

32-bit Microcontroller

NuMicro

Family

NUC123 Series

Datasheet

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Summary of content (99 pages)

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NUC123 ARM® Cortex® -M0 32-bit Microcontroller NuMicro® Family NUC123 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com May 3, 2017 Page 1 of 99 Rev.2.
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NUC123 TABLE OF CONTENTS List of Figures .............................................................................................. 6 List of Tables ............................................................................................... 7 1 GENERAL DESCRIPTION ....................................................................... 8 2 FEATURES ......................................................................................... 9 NuMicro® NUC123 Series Features ...........................
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NUC123 6.3.4 Power-down Mode Clock .................................................................................... 50 6.3.5 Frequency Divider Output ................................................................................... 51 6.4 Flash Memory Controller (FMC) ....................................................................52 6.4.1 Overview ....................................................................................................... 52 6.4.2 Features ....................
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NUC123 6.15 I2S Controller (I2S) ....................................................................................63 6.15.1 Overview ....................................................................................................... 63 6.15.2 Features ........................................................................................................ 63 6.16 USB Device Controller (USB) .......................................................................64 6.16.1 Overview .............
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NUC123 8.4.1 10-bit SARADC Specifications .............................................................................. 87 8.4.2 LDO and Power Management Specifications ............................................................ 88 8.4.3 Low Voltage Reset Specifications .......................................................................... 88 8.4.4 Brown-out Detector Specifications ......................................................................... 89 8.4.
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NUC123 List of Figures ® Figure 4-1 NuMicro NUC123 Series Selection Code ................................................................... 14 ® Figure 4-2 NuMicro NUC123SxxANx LQFP 64-pin Diagram ....................................................... 16 ® Figure 4-3 NuMicro NUC123LxxANx LQFP 48-pin Diagram ....................................................... 17 ® Figure 4-4 NuMicro NUC123ZxxANx QFN 33-pin Diagram .........................................................
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NUC123 List of Tables Table 1-1 Key Features Support Table ............................................................................................ 8 Table 3-1 List of Abbreviations ....................................................................................................... 13 Table 6-1 Reset Value of Registers ............................................................................................... 32 Table 6-2 Power Mode Difference Table ...............................................
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NUC123 1 GENERAL DESCRIPTION ® ® The NuMicro NUC123 series is a new 32-bit Cortex -M0 microcontroller with USB 2.0 Full-speed devices and a 10-bit ADC. The NUC123 series provides the high 72 MHz operating speed, large 20 Kbytes SRAM, 8 USB endpoints and three sets of SPI controllers, which make it powerful in USB communication and data processing.
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NUC123 2 2.1 FEATURES NuMicro® NUC123 Series Features  Core ® ® – ARM Cortex -M0 core runs up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Supports Serial Wire Debug with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranges from 2.5 V to 5.
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NUC123 – 8 selectable time-out period from 1.6ms ~ 26.
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NUC123 – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device Controller – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – S/W override bus  USB 2.0 Full-Speed Device – One set of USB 2.
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NUC123 3 ABBREVIATIONS NUC123 SERIES DATASHEET Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO G
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NUC123 SPS Samples per Second TDES Triple Data Encryption Standard TK Touch Key TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations NUC123 SERIES DATASHEET May 3, 2017 Page 13 of 99 Rev.2.
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NUC123 4 4.
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NUC123 NuMicro® NUC123 Series Selection Guide 4.2 NuMicro® NUC123xxxANx Selection Guide ISP ROM (KB) UART SPI I2C USB LIN PS/2 I2S Comp. PWM ADC RTC EBI ISP\ICP\IAP 1.
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NUC123 NuMicro® NUC123 Series Pin Configuration NuMicro® NUC123xxxANx Pin Diagram ® AVDD ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 VSS PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0 PC.9/SPI1_CLK VDD PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO VSS 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro NUC123SxxANx LQFP 64 pin 48 4.3.1.1 SPI2_SS0/ADC0/PD.0 49 32 PB.9/SPI1_SS1/TM1 SPI0_SS1/SPI2_CLK/ADC1/PD.1 50 31 PB.
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NUC123 ® ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 35 34 33 32 31 30 29 28 27 26 25 NuMicro NUC123LxxANx LQFP 48 pin 36 4.3.1.2 AVDD 37 24 PB.9/SPI1_SS1/TM1 SPI2_SS0/ADC0/PD.0 38 23 PB.10/SPI0_SS1/TM2 SPI0_SS1/SPI2_CLK/ADC1/PD.1 39 22 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 40 21 PC.
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NUC123 ® ICE_CLK ICE_DAT PC.8/SPI1_SS0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 23 22 21 20 19 18 17 NuMicro NUC123ZxxANx QFN 33 pin 24 4.3.1.3 AVDD 25 16 PC.0/SPI0_SS0/I2S_LRCLK SPI0_SS1/SPI2_CLK/ADC1/PD.1 26 15 PC.1/SPI0_CLK/I2S_BCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 27 14 PC.2/SPI0_MISO0/I2S_DI SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 28 13 PC.3/SPI0_MOSI0/I2S_DO XT1_OUT/PF.0 29 12 USB_D+ XT1_IN/PF.
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NUC123 NuMicro® NUC123xxxAEx Pin Diagram ® AVDD ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 VSS PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0/PWM0 PC.9/SPI1_CLK VDD PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO VSS 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro NUC123SxxAEx LQFP 64 pin 48 4.3.2.1 SPI2_SS0/ADC0/PD.0 49 32 PB.9/SPI1_SS1/TM1/PWM1 SPI0_SS1/SPI2_CLK/ADC1/PD.1 50 31 PB.
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NUC123 ® ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0/PWM0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 35 34 33 32 31 30 29 28 27 26 25 NuMicro NUC123LxxAEx LQFP 48 pin 36 4.3.2.2 AVDD 37 24 PB.9/SPI1_SS1/TM1/PWM1 SPI2_SS0/ADC0/PD.0 38 23 PB.10/SPI0_SS1/TM2 SPI0_SS1/SPI2_CLK/ADC1/PD.1 39 22 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 40 21 PC.
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NUC123 ® ICE_CLK ICE_DAT PC.8/SPI1_SS0/PWM0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 23 22 21 20 19 18 17 NuMicro NUC123ZxxAEx QFN 33 pin 24 4.3.2.3 AVDD 25 16 PC.0/SPI0_SS0/I2S_LRCLK SPI0_SS1/SPI2_CLK/ADC1/PD.1 26 15 PC.1/SPI0_CLK/I2S_BCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 27 14 PC.2/SPI0_MISO0/I2S_DI SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 28 13 PC.3/SPI0_MOSI0/I2S_DO XT1_OUT/PF.0 29 12 USB_D+ XT1_IN/PF.
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NUC123 4.4 4.4.1 Pin Description NuMicro® NUC123 Pin Description Pin No LQFP 64- LQFP 48- QFN 33pin pin pin 1 3 3 5* 4 5* Type Description PB.14 I/O INT0 I PB.13 I/O Digital GPIO pin PB.12 I/O Digital GPIO pin SPI1_SS0 I/O SPI1 1st slave select pin CLKO O Frequency Divider output pin PA.11 I/O Digital GPIO pin SPI1_CLK I/O SPI1 serial clock pin SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin I2C1_SCL I/O I2C1 clock pin PA.
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NUC123 13 9 SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin PB.7 I/O Digital GPIO pin UART1_nCTS I SPI2_MISO0 I/O UART1 clear to send input pin SPI2 1st MISO (Master In, Slave Out) pin LDO_CAP P LDO output pin VDD P Power supply for I/O ports and LDO source for internal PLL and digital function. Voltage range is 2.5V ~ 5V. 8 VSS P Ground 13 9 USB_VBUS USB Power supply from USB host or hub 18 14 10 USB_VDD33_CAP USB Internal power regulator output 3.
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NUC123 30 31 32 22 16 23 24 33 34 35 NUC123 SERIES DATASHEET 36 37 40 41 I/O I2S bit clock pin PC.0 I/O Digital GPIO pin SPI0_SS0 I/O SPI0 1st slave select pin I2S_LRCLK I/O I2S left/right channel clock pin PB.10 I/O Digital GPIO pin SPI0_SS1 I/O SPI0 2nd slave select pin TM2 I/O Timer2 event counter input / toggle output pin PB.
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NUC123 42 43 44 45 VSS P Ground PA.14 I/O Digital GPIO pin PWM2 I/O PWM2 PWM output / capture input pin PA.13 I/O Digital GPIO pin PWM1 I/O PWM1 PWM output / capture input pin PA.12 I/O Digital GPIO pin PWM0 I/O PWM0 PWM output / capture input pin Serial wired debugger data pin 32 33 34 46 35 23 ICE_DAT I/O 47 36 24 ICE_CLK I 48 37 25 AVDD AP Power supply for internal analog circuit PD.
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NUC123 57 45 XT1_OUT O External 4~24 MHz high speed crystal output pin PF.1 I/O Digital GPIO pin 30 XT1_IN I External 4~24 MHz high speed crystal input pin nRESET I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up. 59 VSS P Ground 60 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. Voltage range is 2.5 V ~ 5V. PF.
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NUC123 5 5.1 BLOCK DIAGRAM NuMicro® NUC123 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 APROM & DataFlash 36/68 KB ARM Watchdog Timer PDMA Cortex-M0 72MHz LDROM 4 KB SRAM 12/20 KB 10-bit ADC x 8 Windowed Watchdog Timer PWM/Capture Timer x 4 AHB/APB Bus LDO Clock Control Connectivity UART x 2 Power On Reset High Speed Oscillator 22.
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NUC123 6 6.1 FUNCTIONAL DESCRIPTION ARM® Cortex® -M0 Core ® The Cortex -M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA AHB-Lite interface and includes an NVIC component. The processor has optional hardware ® debug functionality, can execute Thumb code, and is compatible with other Cortex -M profile processors. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception.
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NUC123   – 32 external interrupt inputs, each with four levels of priority – Dedicated Non-Maskable Interrupt (NMI) input – Supports both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) with ultra-low power sleep mode Debug support – Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling – Single step and vector catch capabilities Bus interfaces: – Single 32-bit AMBA-3 AHB
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NUC123 6.2 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for 6.2.
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NUC123 Glitch Filter 36 us nRESET ~50k ohm @5v POR_DIS_CODE(PORCR[15:0]) Power-on Reset VDD LVR_EN(BODCR[7]) AVDD Reset Pulse Width 3.2ms Low Voltage Reset BOD_RSTEN(BODCR[3]) Brown-out Reset WDT/WWDT Reset System Reset Reset Pulse Width 64 WDT clocks CHIP Reset CHIP_RST(IPRSTC1[0]) MCU Reset SYSRESETREQ(AIRCR[2]) Software Reset Reset Pulse Width 2 system clocks CPU Reset CPU_RST(IPRSTC1[1]) Figure 6-2 System Reset Resources ® There are a total of 8 reset sources in the NuMicro family.
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NUC123 WDT_S 0x3 0x3 - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - (CLKSEL1[1:0]) XTL12M_STB (CLKSTATUS[0]) PLL_STB (CLKSTATUS[2]) OSC10K_STB (CLKSTATUS[3]) OSC22M_STB (CLKSTATUS[4]) CLK_SW_FAIL (CLKSTATUS[7]) WTE (WTCR[7]) Reload from Reload CONFIG0 from CONFIG0 Reload Reload Reload Reload from from from from CONFIG0 CONFIG0 CONFIG0 CONFIG0 WTCR 0x0700 0x0700 0x0700 0x0700 0x0700 0x
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NUC123 reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will be set to 1 if the previous reset source is nRESET reset. nRESET 0.7 VDD 36 us 0.2 VDD SS 36 us nRESET Reset SS Figure 6-3 shows the nRESET reset waveform. nRESET 0.7 VDD 36 us 0.
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NUC123 Figure 6-4 Power-on Reset (POR) Waveform 6.2.2.3 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset.
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NUC123 AVDD VBODH VBODL Hysteresis T1 T2 (< de-glitch time) (= de-glitch time) BODOUT T3 (= de-glitch time) BODRSTEN Brown-out Reset Figure 6-6 Brown-Out Detector Waveform 6.2.2.5 Watch Dog Timer Reset Software can check if the reset is caused by watch dog time-out to indicate the previous reset is a watch dog reset and handle the failure of MCU after watch dog time-out reset by checking RSTS_WDT (RSTSRC[2]). 6.2.2.
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NUC123 6.2.3 Power modes and Wake-up sources There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the available clocks for each power mode. Power Mode Normal Mode Idle Mode Power-Down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LIRC. SRAM content retended. Entry Condition Chip is in normal mode after system reset released CPU executes WFI instruction.
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NUC123 1. LIRC (10 kHz OSC) ON or OFF depends on Software setting in run mode. 2. If TIMER clock source is selected as LIRC and LIRC is on. 3. If WDT clock source is selected as LIRC and LIRC is on.
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NUC123 WDT WDT Interrupt After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect). UART nCTS wake-up After software writes 1 to clear DCTSF (UA_MSR[0]). I2C Addressing I2C device USB Remote Wake-up After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]). After software writes 1 to clear BUS_STS (USBD_INTSTS[0]). Table 6-4Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral.
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NUC123 6.2.4 System Power Distribution In this chip, power distribution is divided into three segments:  Analog power from AVDD and AVSS provides the power for analog components operation.  Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1.8 V power for digital operation and I/O pins.  USB transceiver power from VBUS offers the power for operating the USB transceiver.
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NUC123 6.2.5 System Memory Map ® The NuMicro NUC123 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the Table 6-5. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on® chip peripherals. The NuMicro NUC123 Series only supports little-endian data format.
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NUC123 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6-5 Address Space Assignments for On-Chip Controllers NUC123 SERIES DATASHEET May 3, 2017 Page 41 of 99 Rev.2.
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NUC123 6.2.6 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
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NUC123 6.2.7 Nested Vectored Interrupt Controller (NVIC) ® Cortex -M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”.
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NUC123 6.2.7.1 Exception Model and System Interrupt Map ® Table 6-6 lists the exception model supported by the NuMicro NUC123 Series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest userconfigurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “0”.
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NUC123 31 15 SPI1_INT SPI1 SPI1 interrupt 32 16 SPI2_INT SPI2 SPI2 interrupt 33 17 Reserved Reserved 2 Reserved 34 18 I2C0_INT I C0 I2C0 interrupt 35 19 I2C1_INT I2C1 I2C1 interrupt 36 20 Reserved Reserved Reserved 37 21 Reserved Reserved Reserved 38 22 Reserved Reserved Reserved 39 23 USB_INT USBD USB 2.
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NUC123 6.2.7.2 Vector Table When any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers.
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NUC123 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters ® Power-down mode when Cortex -M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
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NUC123 XTL12M_EN (PWRCON[0]) XT1_OUT HXT 4~24 MHz HXT PLL_SRC (PLLCON[19]) XT1_IN 0 OSC22M_EN (PWRCON[2]) PLL PLL FOUT 1 22.1184 MHz HIRC HIRC OSC10K_EN (PWRCON[3]) LIRC 10 kHz LIRC Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
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NUC123 LIRC (10 kHz) HIRC 111 LIRC 010 1/2 HXT CPUCLK 011 PLLFOUT HIRC (22.
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NUC123 6.3.2 System Clock and SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown in Figure 6-11. HIRC (22.
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NUC123  6.3.5 WDT/Timer/PWM Peripherals Clock (when 10 kHz intertnal low speed RC oscillator (LIRC) is adopted as clock source) Frequency Divider Output This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin.
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NUC123 6.4 Flash Memory Controller (FMC) 6.4.1 Overview ® The NuMicro NUC123 series is equipped with 68/36 Kbytes on-chip embedded flash for application program memory (APROM) and Data Flash, and 4 Kbytes for ISP loader program memory (LDROM) that could be programmed boot loader to update APROM and Data Flash through In-System-Programming (ISP) procedure. The ISP function enables user to update ® embedded flash when chip is soldered on PCB.
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NUC123 6.5 General Purpose I/O (GPIO) 6.5.1 Overview ® The NuMicro NUC123 series has up to 47 General Purpose I/O pins shared with other function pins depending on the chip configuration. These 47 pins are arranged in 5 ports named GPIOA, GPIOB, GPIOC, GPIOD and GPIOF. GPIOA has 6 pins on PA[15:10]. GPIOB has 15 pins on PB[15:12] and PB[10:0]. GPIOC has 12 pins on PC[13:8] and PC[5:0]. GPIOD has 10 pins on PD[11:8] and PD[5:0]. GPIOF has 4 pins on PF[3:0].
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NUC123 6.6 PDMA Controller (PDMA) 6.6.1 Overview ® The NuMicro NUC123 contains a six-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA can transfer data to and from memory or transfer data to and from APB devices. For PDMA channel (PDMA CH0~CH5), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory.
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NUC123 6.7 Timer Controller (TMR) 6.7.1 Overview The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.7.
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NUC123 6.8 PWM Generator and Capture Timer (PWM) 6.8.1 Overview ® The NuMicro NUC123 series has 1 set of PWM group supporting 1 set of PWM generators which can be configured as 4 independent PWM outputs, PWM0~PWM3, or as 2 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) with two programmable dead-zone generators. PWM output function can be alternated to capture function.
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NUC123 6.9 Watchdog Timer (WDT) 6.9.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.9.2 Features  18-bit free running up counter for WDT time-out interval  Selectable time-out interval (2 ~ 2 ) and the time-out interval is 1.6 ms ~ 26.214 s if WDT_CLK = 10 kHz.
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NUC123 6.10 Window Watchdog Timer (WWDT) 6.10.1 Overview The Window Watchdog Timer is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. The 6-bit down counter value will stop to update when chip is in Idle or Power-down mode. 6.10.
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NUC123 6.11 UART Interface Controller (UART) 6.11.1 Overview ® The NuMicro NUC123 series provides two channels of Universal Asynchronous Receiver/ Transmitters (UART). UART Controller performs Normal Speed UART and supports flow control function. The UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports six types of interrupts.
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NUC123 6.12 PS/2 Device Controller (PS2D) 6.12.1 Overview PS/2 device controller provides basic timing control for PS/2 communication. All communication between the device and the host is managed through the CLK and DATA pins. Unlike PS/2 keyboard or mouse device controller, the received/transmit code needs to be translated as meaningful code by firmware. The device controller generates the CLK signal after receiving a request to send, but host has ultimate control over communication.
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NUC123 6.13 I2C Serial Interface Controller (Master/Slave) (I2C) 6.13.1 Overview 2 I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data 2 exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. 2 There are two sets of I C controllers which support Power-down wake-up function. 6.13.
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NUC123 6.14 Serial Peripheral Interface (SPI) 6.14.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction ® interface. This NuMicro NUC123 series contains up to three sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
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NUC123 6.15 I2S Controller (I2S) 6.15.1 Overview The I2S controller consists of IIS protocol to interface with external audio CODEC. Two 8 word depth FIFO buffers for read path and write path respectively and is capable of handling 8/16/24/32 bits word sizes. PDMA controller handles the data movement between FIFO and memory. 6.15.
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NUC123 6.16 USB Device Controller (USB) 6.16.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/ Isochronous transfer types. In this device controller, there are two main interfaces: APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it.
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NUC123 6.17 Analog-to-Digital Converter (ADC) 6.17.1 Overview ® NuMicro NUC123 Series contains one 10-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converters can be started by software, PWM center-aligned trigger and external STADC pin. 6.17.
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NUC123 7 ELECTRICAL CHARACTERISTICS (NUC123XXXANX) 7.1 Absolute Maximum Ratings Symbol VDD  VSS VIN 1/tCLCL Parameter DC Power Supply Input Voltage Oscillator Frequency Min Max Unit -0.3 +7.0 V VSS - 0.3 VDD + 0.
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NUC123 7.2 DC Electrical Characteristics (VDD -VSS = 5.5 V, TA = 25C) SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT 5.5 V Operation voltage VDD 2.5 VDD rise rate to ensure internal operation correctly VRISE 0.05 V/ms -0.3 V Power ground VSS AVSS LDO output voltage VLDO 1.62 1.8 Analog operating voltage AVDD 0 1.98 VDD = 2.5V ~ 5.5V up to 72 MHz V VDD > 2.5V VDD V When system uses analog function, please refer to chapter 7.
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NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT at 4 MHz VDD = 5V at 4 MHz, IDD10 3 mA IDD11 4 mA IDD12 2 mA IIDLE1 29 mA IIDLE2 14 mA IIDLE3 28 mA IIDLE4 13 mA IIDLE5 6 mA IIDLE6 3 mA IIDLE7 5 mA IIDLE8 2 mA IIDLE9 3 mA IIDLE10 2 mA IIDLE11 2 mA IIDLE12 1 mA All IP and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP and PLL Disabled, XTAL = 4 MHz VDD = 5.
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NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT VDD = 5.5V at 10 kHz, IIDLE5 131 uA IIDLE6 129 uA IIDLE7 125 uA IIDLE8 124 uA IPWD1 12 A IPWD2 9 A Input Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional mode) IIN1 -64 A VDD = 5.5V, VIN = 0V or VIN = VDD Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 A VDD = 5.
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NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT ISR11 -300 -370 -450 A VDD = 4.5V, VS = 2.4V ISR12 -50 -70 -90 A VDD = 2.7V, VS = 2.2V ISR12 -40 -60 -80 A VDD = 2.5V, VS = 2.0V ISR21 -20 -24 -28 mA VDD = 4.5V, VS = 2.4V ISR22 -4 -6 -8 mA VDD = 2.7V, VS = 2.2V ISR22 -3 -5 -7 mA VDD = 2.5V, VS = 2.0V ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V ISK1 7 10 13 mA VDD = 2.7V, VS = 0.45V ISK1 6 9 12 mA VDD = 2.5V, VS = 0.
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NUC123 7.3 AC Electrical Characteristics 7.3.1 External 4~24 MHz High Speed Oscillator tCLCL tCLCH 0.7 VDD 90% tCLCX 10% 0.3 VDD tCHCL tCHCX Note: Duty cycle is 50%. SYMBOL PARAMETER tCHCX MIN TYP MAX UNIT Clock High Time 10 - - nS tCLCX Clock Low Time 10 - - nS tCLCH Clock Rise Time 2 - 15 nS tCHCL Clock Fall Time 2 - 15 nS CONDITIONS MIN TYP MAX UNIT External crystal 4 12 24 MHz Temperature - -40 - 85 ℃ VDD - 2.5 5 5.5 V 7.3.
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NUC123 7.3.3 Internal 22.1184 MHz High Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 22.1184 - MHz +25℃; VDD =5 V -1 - +1 % -3 - +3 % VDD =5 V - 500 - uA CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 10 - kHz +25℃; VDD =5 V -30 - +30 % -50 - +50 % Calibrated Internal Oscillator Frequency -40℃~+85℃; VDD =2.5 V~5.5 V Operation Current 7.3.
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NUC123 7.4 Analog Characteristics 7.4.1 10-bit SARADC Specifications SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP 2.7 MAX UNIT 5.5 V AVDD = VDD AVDD = VDD = 5V, FSPS = 150K Operating Voltage AVDD Operating Current IADC 1.
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NUC123 7.4.2 LDO and Power Management Specifications PARAMETER MIN TYP MAX UNIT NOTE Input Voltage 2.5 5 5.5 V VDD input voltage Output Voltage 1.62 1.8 1.98 V VDD > 2.5V Temperature -40 25 85 ℃ Cbp - 1 - uF Resr = 1Ω Notes: 1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between V DD and the closest VSS pin of the device. 2.
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NUC123 7.4.4 Brown-out Detector Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AVDD = 5.5 V - - 125 μA Temperature - -40 25 85 ℃ BOV_VL[1:0] = 11 4.4 4.5 4.6 V BOV_VL [1:0] = 10 3.7 3.8 3.9 V BOV_VL [1:0] = 01 2.6 2.7 2.8 V BOV_VL [1:0] = 00 2.1 2.2 2.
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NUC123 7.4.6 USB PHY Specifications 7.4.6.1 USB DC Electrical Characteristics SYMBOL PARAMETER VIH Input high (driven) VIL Input low VDI Differential input sensitivity VCM VSE CONDITIONS MIN TYP MAX UNIT 2.0 V 0.8 Differential common-mode range V |PADP-PADM| 0.2 Includes VDI range 0.8 2.5 V 0.8 2.0 V Single-ended receiver threshold Receiver hysteresis V 200 mV VOL Output low (driven) 0 0.3 V VOH Output high (driven) 2.8 3.6 V VCRS Output signal cross voltage 1.
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NUC123 Cbp 7.5 External Bypass Capacitor 1.0 - uF Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.62 1.8 1.98 V[1] VDD Supply voltage TRET Data Retention TERASE Page Erase Time 20 ms TMER Mass Erase Time 40 ms TPROG Program Time 40 us IDD1 Read Current IDD2 Program/Erase Current IPD Power Down Current Temp=85 ℃ 10 year 1 0.25 mA 7 mA 20 uA Note: VDD is source from chip LDO output voltage.
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NUC123 7.6 SPI Dynamic Characteristics SYMBOL PARAMETER MIN TYP MAX UNIT SPI Master mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor) tDS Data setup time TBD TBD - ns tDH Data hold time TBD - - ns tV Data output valid time - TBD TBD ns SPI Master mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor) tDS Data setup time TBD TBD - ns tDH Data hold time TBD - - ns tV Data output valid time - TBD TBD ns SPI Slave mode (VDD = 4.5V ~ 5.
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NUC123 CLKP=0 SPICLK CLKP=1 tDS MOSI Data Valid tDH Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tv MISO Data Valid tDS MOSI Data Valid tDH Data Valid Data Valid Data Valid Data Valid tv MISO CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 Figure 7-3 SPI Slave Dynamic Characteristics Timing NUC123 SERIES DATASHEET May 3, 2017 Page 79 of 99 Rev.2.
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NUC123 8 ELECTRICAL CHARACTERISTICS (NUC123XXXAEX) 8.1 Absolute Maximum Ratings Symbol VDD  VSS VIN 1/tCLCL Parameter DC Power Supply Input Voltage Oscillator Frequency Min Max Unit -0.3 +7.0 V VSS - 0.3 VDD + 0.
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NUC123 8.2 DC Electrical Characteristics (VDD-VSS=2.5 ~ 5.5 V, TA = 25C) SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT 5.5 V Operation voltage VDD 2.5 VDD rise rate to ensure internal operation correctly VRISE 0.05 V/ms -0.3 V Power ground VSS AVSS LDO output voltage VLDO 1.62 1.8 1.98 V Analog operating voltage AVDD 0 VDD V IDD1 39 mA IDD2 24 mA IDD3 37 mA IDD4 23 mA IDD5 10 mA IDD6 7 mA IDD7 8 mA IDD8 6 mA VDD = 2.5V ~ 5.
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NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT at 4 MHz VDD = 5V at 4 MHz, IDD10 5 mA IDD11 4 mA IDD12 3 mA IIDLE1 28 mA IIDLE2 12 mA IIDLE3 25 mA IIDLE4 10 mA IIDLE5 6 mA IIDLE6 3 mA IIDLE7 5 mA IIDLE8 2 mA IIDLE9 5 mA IIDLE10 4 mA IIDLE11 3 mA IIDLE12 2 mA All IP and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP and PLL Disabled, XTAL = 4 MHz VDD = 5.
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NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT VDD = 5.5V at 10 kHz, IIDLE5 110 uA IIDLE6 110 uA IIDLE7 100 uA IIDLE8 100 uA IPWD1 15 A IPWD2 13 A Input Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional mode) IIN1 -64 A VDD = 5.5V, VIN = 0V Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 A VDD = 5.
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NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT ISR11 -300 -370 -450 A VDD = 4.5V, VS = 2.4V ISR12 -50 -70 -90 A VDD = 2.7V, VS = 2.2V ISR12 -40 -60 -80 A VDD = 2.5V, VS = 2.0V ISR21 -24 -28 -32 mA VDD = 4.5V, VS = 2.4V ISR22 -4 -6 -8 mA VDD = 2.7V, VS = 2.2V ISR22 -3 -5 -7 mA VDD = 2.5V, VS = 2.0V ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V ISK1 7 10 13 mA VDD = 2.7V, VS = 0.45V ISK1 6 9 12 mA VDD = 2.5V, VS = 0.
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NUC123 8.3 AC Electrical Characteristics 8.3.1 External 4~24 MHz High Speed Oscillator tCLCL tCLCH 0.7 VDD 90% tCLCX 10% 0.3 VDD tCHCL tCHCX Note: Duty cycle is 50%. SYMBOL PARAMETER tCHCX MIN TYP MAX UNIT Clock High Time 10 - - nS tCLCX Clock Low Time 10 - - nS tCLCH Clock Rise Time 2 - 15 nS tCHCL Clock Fall Time 2 - 15 nS CONDITIONS MIN TYP MAX UNIT External crystal 4 - 24 MHz Temperature - -40 - 105 ℃ VDD - 2.5 - 5.5 V 8.3.
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NUC123 8.3.3 Internal 22.1184 MHz High Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 22.1184 - MHz +25℃; VDD =5 V -1 - +1 % -3 - +3 % VDD =5 V - 500 - uA CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 10 - kHz +25℃; VDD =5 V -30 - +30 % -50 - +50 % Calibrated Internal Oscillator Frequency -40℃~+105℃; VDD=2.5 V~5.5 V Operation Current 8.3.
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NUC123 8.4 8.4.1 Analog Characteristics 10-bit SARADC Specifications Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Unit 5.5 V Operating voltage AVDD Operating current IADC 1.5 mA Resolution RADC 10 bit Reference voltage VREF ADC input voltage VIN 0 Sampling rate FSPS 200K Integral non-linearity error 2.7 Max.
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NUC123 8.4.2 LDO and Power Management Specifications PARAMETER MIN TYP MAX UNIT NOTE Input Voltage 2.5 5 5.5 V VDD input voltage Output Voltage 1.62 1.8 1.98 V VDD > 2.5V Temperature -40 25 105 ℃ Cbp - 1 - uF Resr = 1Ω Notes: 1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between V DD and the closest VSS pin of the device. 2.
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NUC123 8.4.4 Brown-out Detector Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AVDD = 5.5 V - - 125 μA Temperature - -40 25 105 ℃ BOV_VL[1:0] = 11 4.2 4.4 4.6 V BOV_VL [1:0] = 10 3.5 3.7 3.9 V BOV_VL [1:0] = 01 2.6 2.7 2.8 V BOV_VL [1:0] = 00 2.1 2.2 2.
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NUC123 8.4.6 USB PHY Specifications 8.4.6.1 USB DC Electrical Characteristics SYMBOL PARAMETER VIH Input high (driven) VIL Input low VDI Differential input sensitivity VCM VSE CONDITIONS MIN TYP MAX UNIT 2.0 V 0.8 Differential common-mode range V |PADP-PADM| 0.2 Includes VDI range 0.8 2.5 V 0.8 2.0 V Single-ended receiver threshold Receiver hysteresis V 200 mV VOL Output low (driven) 0 0.3 V VOH Output high (driven) 2.8 3.6 V VCRS Output signal cross voltage 1.
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NUC123 Cbp External Bypass Capacitor 1.0 - uF NUC123 SERIES DATASHEET May 3, 2017 Page 91 of 99 Rev.2.
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NUC123 8.5 Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.62 1.8 1.98 V[1] VDD Supply Voltage NENDUR Endurance TRET Data Retention TERASE Page Erase Time 20 ms TMER Mass Erase Time 40 ms TPROG Program Time 35 μs IDD1 Read Current TBD mA/MHz IDD2 Program/Erase Current IPD Power Down Current At 25℃ 20000 cycles[2] 100 year - - 1 7 mA 20 μA Note1: VDD is source from chip LDO output voltage.
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NUC123 8.6 SPI Dynamic Characteristics SYMBOL PARAMETER MIN TYP MAX UNIT SPI Master mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor) tDS Data setup time 4 2 - ns tDH Data hold time 0 - - ns tV Data output valid time - 7 11 ns SPI Master mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor) tDS Data setup time 5 3 - ns tDH Data hold time 0 - - ns tV Data output valid time - 13 18 ns SPI Slave mode (VDD = 4.5V ~ 5.
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NUC123 CLKP=0 SPICLK CLKP=1 tDS MOSI Data Valid tDH Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tv MISO Data Valid tDS MOSI Data Valid tDH Data Valid Data Valid Data Valid Data Valid tv MISO CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 Figure 8-3 SPI Slave Dynamic Characteristics Timing NUC123 SERIES DATASHEET May 3, 2017 Page 94 of 99 Rev.2.
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NUC123 9 9.1 PACKAGE DIMENSIONS 64L LQFP (7x7x1.4 mm footprint 2.0 mm) NUC123 SERIES DATASHEET May 3, 2017 Page 95 of 99 Rev.2.
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NUC123 9.2 48L LQFP (7x7x1.4 mm footprint 2.0 mm) NUC123 SERIES DATASHEET May 3, 2017 Page 96 of 99 Rev.2.
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NUC123 9.3 33L QFN (5x5x0.8 mm) 32 25 1 24 8 17 9 16 25 32 24 1 17 8 May 3, 2017 9 NUC123 SERIES DATASHEET 16 Page 97 of 99 Rev.2.
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NUC123 10 REVISION HISTORY Date Revision Description 2012.04.01 1.00 Preliminary version. 2015.05.29 2.00 1. Merged NUC123xxxANx & NUC123xxxAEx into this document. 2015.11.04 2.01 1. Removed ADC function pins of NUC123 QFN33 package type in section 4.3.1.3, 4.3.2.3 and 4.4.1. 2016.01.12 2.02 1. Revised section 8.2 Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode). 2016.07.06 2.03 1. Updated ADC function pins of NUC123 QFN33 package type in section 4.3.1.3, 4.3.2.3 and 4.4.1. 2017.05.
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NUC123 Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.