Data Sheet

MPR121 Sensor
24 Freescale Semiconductor
Operation with Multiple Masters
The application should use repeated starts to address the MPR121 to avoid bus confusion between I
2
C masters. On an I
2
C
bus, once a master issues a start/repeated start condition, that master owns the bus until a stop condition occurs. If a master that
does not own the bus attempts to take control of that bus, then improper addressing may occur. An address may always be
rewritten to fix this problem. Follow I
2
C protocol for multiple master configurations.
MPR121 Slave Address and R/W bit
MPR121 use a 7-bit format slave address which is pin configurable by ADDR pin connection. The MPR121 slave addresses
can be configured as shown in Table 7.
Table 7.
ADDR Pin Connection
I
2
C Address
VDD
0x5A
VSS
0x5B
SDA
0x5C
SCL
0x5D
The MPR121 monitors the bus continuously, waiting for a START condition followed by its slave address. The bit following the
7-bit slave address (the 8
th
bit) is the R/W bit, which is low for a write command and high for a read command (Figure 9). When
a MPR121 recognizes its slave address, it acknowledges and is then ready for continued communication.
SDA
1 0 1
MSB
1 0 1 0 R/W ACK
SCL
Figure 9. Slave Address
Acknowledge
The acknowledge bit is a clocked 9
th
bit (Figure 11) which the recipient uses to handshake receipt of each byte of data. Thus
each byte transferred effectively requires 9 bits. The master generates the 9
th
clock pulse, and the recipient pulls down SDA
during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the
master is transmitting to the MPR121, the MPR121 generates the acknowledge bit, since the MPR121 is the recipient. When the
MPR121 is transmitting to the master, the master generates the acknowledge bit, since the master is the recipient.
START
CONDITION
SCL
CLOCK PULSE FOR
ACKNOWLEDGEMENT
1 2 8 9
SDA
BY TRANSMITTER
SDA
BY RECEIVER
S
Figure 10. Acknowledge