Data Sheet

MPR121 Sensor
18 Freescale Semiconductor
14. GPIO Registers (0x73~0x7A)
These registers control GPIO function. D7~D0 bits corresponds to GPIO7 ~ GPIO0 on pins ELE11/LED7 ~ ELE4/LED0
respectively. The GPIO control registers can write always regardless Stop and Run mode. The configuration of the LED driver
and GPIO system is described with more detail in application note AN3894.
When the ports are not used for electrode sensing, they can be used for GPIO pins to be set as input or output, and can be
used to drive LED.
Note: The number of touch sensing electrodes, and therefore the number of GPIO ports left available is configured by the
Electrode Configuration register (0x5E) and GPIO Enable Register (0x77), but electrode configuration has higher priority than
GPIO feature. When a pin is enabled as GPIO but is also selected as electrode by Electrode Configuration Register, the GPIO
function is disabled immediately and it becomes an electrode during Run Mode.
During the Stop Mode just after power on reset, all electrodes and GPIO ports are in high impedance as all the GPIO ports and
are default disabled and the electrodes are not enabled.
GPIO Registers
(0x73~0x7A)
Name
Address
D7
D6
D5
D4
D3
D2
D1
D0
GPIO Control 0
0x73
CTL0[7]
CTL0[6]
CTL0[5]
CTL0[4]
CTL0[3]
CTL0[2]
CTL0[1]
CTL0[0]
GPIO Control 1
0x74
CTL1[7]
CTL1[6]
CTL1[5]
CTL1[4]
CTL1[3]
CTL1[2]
CTL1[1]
CTL1[0]
GPIO Data
0x75
DAT[7]
DAT[6]
DAT[5]
DAT[4]
DAT[3]
DAT[2]
DAT[1]
DAT[0]
GPIO Direction
0x76
DIR[7]
DIR[6]
DIR[5]
DIR[4]
DIR[3]
DIR[2]
DIR[1]
DIR[0]
GPIO Enable
0x77
EN[7]
EN[6]
EN[5]
EN[4]
EN[3]
EN[2]
EN[1]
EN[0]
GPIO Data Set
0x78
SET[7]
SET[6]
SET[5]
SET[4]
SET[3]
SET[2]
SET[1]
SET[0]
GPIO Data Clear
0x79
CLR[7]
CLR[6]
CLR[5]
CLR[4]
CLR[3]
CLR[2]
CLR[1]
CLR[0]
GPIO Data Toggle
0x7A
TOG[7]
TOG[6]
TOG[5]
TOG[4]
TOG[3]
TOG[2]
TOG[1]
TOG[0]
EN, DIR, CTL0, CTL1: GPIO Enable and Input/Output Configuration Bits
When an EN bit sets, the corresponding GPIO pin is enabled and the function is configured by CTL0, CTL1 and DIR bits.
When the port is used as input, it can be configured as normal logic input with high impedance (CTL0CTL1=2b00) or input with
additional internal pull-down (CTL0CTL1=2b10) or pull-up (CTL0CTL1=2b11), note the former may result unstable logic input
state if opened without fixed logic level input.
For output configuration, it can be push/pull (CTL0CTL1=2b00) or open drain.
EN
DIR
CTL0:CTL1
DESCRIPTION
0
X
XX
GPIO function is disabled. Port is high impedance state if not enabled for
electrode either.
1
0
00
GPIO port becomes input port.
1
0
10
GPIO port becomes input port with internal pull-down.
1
0
11
GPIO port becomes input port with internal pull-up.
1
0
01
Not defined yet (as same as CTL0:CTL1 = 00).
1
1
00
GPIO port becomes CMOS output port.
1
1
11
GPIO port becomes open drain output port with only high side MOS.
1
1
10
GPIO port becomes open drain output port with only low side MOS.
1
1
01
Not defined yet (as same as CTL0:CTL1 = 00).
DAT: GPIO Data bits
When a GPIO is enabled as output, the GPIO port outputs the corresponding DAT bit level from GPIO Data Register (0x075).
The output level toggle holds on during any electrode charging and AD conversion and the level transition will be occurred
after the AD conversion. Reading this register returns the content of the GPIO Data Register (not a level of the port).
When a GPIO is configured as input, reading this register returns latched input level of the corresponding port (not contents of
the GPIO Data Register). A write changes content of the register, but not affect to the input function.
SET, CLR, TOG: Manipulate GPIO Data Register Content