User's Manual

5 4 3 2 1
D
C
B
A
A
(smp_on_rst[8])
(smp_on_rst[0])
(smp_on_rst[5])
(smp_on_rst[1])
(smp_on_rst[2])
(smp_on_rst[3])
(smp_on_rst[4])
(smp_on_rst[6])
(smp_on_rst[9])
(smp_on_rst[7])
Sample on reset configuration
Debug test points
Debug test points
Debug
test
point
WHDI_D0
WHDI_DE
WHDI_V_SYNC
WHDI_H_SYNC
WHDI_SPDIF
WHDI_I2S_D0
WHDI_LRCLK
WHDI_SCLK
WHDI_DCLK
WHDI_I2S_D1
WHDI_I2S_D2
WHDI_I2S_D3
WHDI_MCLK
WHDI_D1
WHDI_D2
WHDI_D3
WHDI_D4
WHDI_D5
WHDI_D6
WHDI_D7
WHDI_D8
WHDI_D9
WHDI_D10
WHDI_D11
WHDI_D12
WHDI_D13
WHDI_D14
WHDI_D15
WHDI_D16
WHDI_D17
WHDI_D18
WHDI_D19
WHDI_D20
WHDI_D21
WHDI_D22
WHDI_D23
WHDI_D24
WHDI_D25
WHDI_D26
WHDI_D27
WHDI_D28
WHDI_D29
WHDI_D30
WHDI_D31
WHDI_D32
WHDI_D33
WHDI_D34
WHDI_D35
WHDI_D[35..0] 10
WHDI_DCLK 10
WHDI_DE 10
WHDI_V_SYNC 10
WHDI_H_SYNC 10
WHDI_DCLK 10
WHDI_I2S_D[3..0] 10
WHDI_SPDIF 10
WHDI_MCLK 10
WHDI_SCLK 10
WHDI_LRCLK 10
3.3V_SHACHAF
FLASH_SPI_CLK 4
FLASH_SPI_MOSI 4
FLASH_SPI_SS 4
PA_ENABLE 2,7
RFSPI_DOUT 2,8
RFSPI_CLK 2,8
RFSPI_CS 2,8
WHDI_REF_CLK_OUT 4,11
UL_RX_ANT_SEL_N 2
UL_RX_ANT_SEL_P 2
Title
Size Document Number Rev
Date: Sheet
of
Dfine
2431.01-JD7.820.271 1.0
SHACHAF AV
Dfine
Building A2,Tianfu Software Park,Hi-tech Zone
South Extension of Tianfu Wide Road
Chengdu
China
A4
311Monday, October 18, 2010
Title
Size Document Number Rev
Date: Sheet
of
Dfine
2431.01-JD7.820.271 1.0
SHACHAF AV
Dfine
Building A2,Tianfu Software Park,Hi-tech Zone
South Extension of Tianfu Wide Road
Chengdu
China
A4
311Monday, October 18, 2010
Title
Size Document Number Rev
Date: Sheet
of
Dfine
2431.01-JD7.820.271 1.0
SHACHAF AV
Dfine
Building A2,Tianfu Software Park,Hi-tech Zone
South Extension of Tianfu Wide Road
Chengdu
China
A4
311Monday, October 18, 2010
R?NCR0402 R?NCR0402
12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
R113NCR0402 R113NCR0402
12
TP70 TP_SMD_ROUND
W_12_24_40
TP70 TP_SMD_ROUND
W_12_24_40
TP? TP_SMD_ROUND
W_12_24_40
TP? TP_SMD_ROUND
W_12_24_40
R?NCR0402 R?NCR0402
12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
R?NCR0402 R?NCR0402
12
R112NCR0402 R112NCR0402
12
TP? TP_SMD_ROUND W_12_24_40TP? TP_SMD_ROUND W_12_24_40
R?3.9KohmR04021% R?3.9KohmR04021%
12
TP? TP_SMD_ROUND W_12_24_40TP? TP_SMD_ROUND W_12_24_40
R?NCR0402 R?NCR0402
12
R?NCR0402 R?NCR0402
12
TP? TP_SMD_ROUND W_12_24_40TP? TP_SMD_ROUND W_12_24_40
R1203.9KohmR0402 1% R1203.9KohmR0402 1%
12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
R?NCR0402 R?NCR0402
12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
R?NCR0402 R?NCR0402
12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
U9B
AMN2120_A4
BGA169_P08MM
U9B
AMN2120_A4
BGA169_P08MM
DCLK_I
N2
VD_0
M13
VD_1
N13
VD_2
L12
VD_3
M12
VD_4
N12
VD_5
K11
VD_6
L11
VD_7
M11
VD_8
N11
VD_9
K10
VD_10
L10
VD_11
M10
VD_12
N10
VD_13
N8
VD_14
K9
VD_15
L9
VD_16
N9
VD_17
M7
VD_18
M9
VD_19
K8
VD_20
L8
VD_21
N7
VD_22
L7
VD_23
M8
VD_24
K7
VD_25
K6
VD_26
M6
VD_27
N6
VD_28
L6
VD_29
L5
VD_30
M5
VD_31
K5
VD_32
N5
VD_33
K4
VD_34
L4
VD_35
M4
HSYNC_I
M3
VSYNC_I
N3
DE_I
N4
I2S_MCK
L13
I2S_SCK
H13
I2S_WS
K13
I2S_SD_0
J13
I2S_SD_1
J12
I2S_SD_2
J11
I2S_SD_3
K12
SPDIF_D
H12
R?3.9KohmR0402 1% R?3.9KohmR0402 1%
12
R?NCR0402 R?NCR0402
12
R1213.9KohmR0402 1% R1213.9KohmR0402 1%
12