User`s manual

www.dfi .comChapter 3 Hardware Installation
25
Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance CR960 Carrier Board Description
LVDS_A0+ A71
LVDS_A0- A72
LVDS_A1+ A73
LVDS_A1- A74
LVDS_A2+ A75
LVDS_A2- A76
LVDS_A3+ A78
LVDS_A3- A79
LVDS_A_CK+ A81
LVDS_A_CK- A82
LVDS_B0+ B71
LVDS_B0- B72
LVDS_B1+ B73
LVDS_B1- B74
LVDS_B2+ B75
LVDS_B2- B76
LVDS_B3+ B77
LVDS_B3- B78
LVDS_B_CK+ B81
LVDS_B_CK- B82
LVDS_VDD_EN A77 O CMOS 3.3V / 3.3V PD 100K to GND
Connect to enable control of LVDS
p
anel
p
ower
circuit
LVDS panel power enable
LVDS_BKLT_EN B79 O CMOS 3.3V / 3.3V PD 100K to GND
Connect to enable control of LVDS panel backlight
p
ower circuit.
LVDS panel backlight enable
LVDS_BKLT_CTRL B83 O CMOS 3.3V / 3.3V PD 100K to GND
Connect to brightness control of LVDS panel
backli
g
ht
p
ower circuit.
LVDS panel backlight brightness control
LVDS_I2C_CK A83 I/O OD CMOS 3.3V / 3.3V PU 2.2K to 3.3V Connect to DDC clock of LVDS panel I2C clock output for LVDS display use
LVDS_I2C_DAT A84 I/O OD CMOS 3.3V / 3.3V PU 2.2K to 3.3V Connect to DDC data of LVDS panel I2C data line for LVDS display use
Signal Pin# Pin Type Pwr Rail /Tolerance CR960 Carrier Board Description
LPC_AD0 B4
LPC_AD1 B5
LPC_AD2 B6
LPC_AD3 B7
LPC_FRAME# B3 O CMOS 3.3V / 3.3V LPC frame indicates the start of an LPC cycle
LPC_DRQ0# B8
LPC_DRQ1# B9
LPC_SERIRQ A50 I/O CMOS 3.3V / 3.3V PU 10K to 3.3V LPC serial interrupt
LPC_CLK B10 O CMOS 3.3V / 3.3V LPC clock output - 33MHz nominal
ȟ
ȟ
ȟ
ȟ
3.3V / 3.3V LPC serial DMA request
LVDS Channel B differential clock
O LVDS LVDS Connect to LVDS connector
Connect to LVDS connector
LVDS Channel A differential clockO LVDS LVDS Connect to LVDS connector
O LVDS
O LVDS LVDS Connect to LVDS connector
O LVDS LVDS Connect to LVDS connector
I/O CMOS 3.3V / 3.3V
LPC Si
g
nals Descri
p
tion
s
Connect to LPC device
LVDS Channel B differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LVDS_A_CK+/-,
LVDS_B_CK+/-) shall have 100ƻ terminations across the pairs at the destination. These
terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer
on-board
I CMOS
LVDS Si
g
nals Descri
p
tion
s
O LVDS LVDS Connect to LVDS connector
LVDS Channel A differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LVDS_A_CK+/-,
LVDS_B_CK+/-) shall have 100ƻ terminations across the pairs at the destination. These
terminations may be on the Carrier Board if the Carrier Board implements a LVDS deserializer
on-board
O LVDS Connect to LVDS connector
O LVDS LVDS
Connect to LVDS connector
LVDS
LVDS
Connect to LVDS connector
O LVDS LVDS
LPC multiplexed address, command and data bus
O LVDS LVDS Connect to LVDS connector