User`s manual

www.dfi .comChapter 3 Hardware Installation
18
Chapter 3
Si
g
nal Pin# Pin T
yp
e Pwr Rail
/
Tolerance PU
/
PD Descri
p
tion
IDE
_
D0 D7
IDE
_
D1 C10
IDE
_
D2 C8
IDE
_
D3 C4
IDE
_
D4 D6
IDE
_
D5 D2
IDE
_
D6 C3
IDE
_
D7 C2 PD 10
K
IDE
_
D8 C6
IDE
_
D9 C7
IDE
_
D10 D3
IDE
_
D11 D4
IDE
_
D12 D5
IDE
_
D13 C9
IDE
_
D14 C12
IDE
_
D15 C5
IDE
_
A0 D13
IDE
_
A1 D14
IDE
_
A2 D15
IDE
_
IOW# D9 O CMOS 3.3V
/
3.3
V
I
/
O write line to IDE device. Data latched on trailin
g(
risin
g)
ed
g
e.
IDE
_
IOR# C14 O CMOS 3.3V
/
3.3
V
I
/
O read line to IDE device.
IDE
_
RE
Q
D8 I CMOS 3.3V
/
5
V
PD 5.6
K
IDE Device DMA Re
q
uest. It is asserted b
y
the IDE device to re
q
uest a data transfer.
IDE
_
ACK# D10 O CMOS 3.3V
/
3.3
V
IDE Device DMA Acknowled
g
e.
IDE
_
CS1# D16 O CMOS 3.3V
/
3.3
V
IDE Device Chi
p
Select for 1F0h to 1FFh ran
g
e.
IDE
_
CS3# D17 O CMOS 3.3V
/
3.3
V
IDE Device Chi
p
Select for 3F0h to 3FFh ran
g
e.
IDE
_
IORDY C13 I CMOS 3.3V
/
5
V
PU 4.7k to 3.3
V
IDE device I
/
O read
y
in
p
ut. Pulled low b
y
the IDE device to extend the c
y
cle.
IDE
_
RESET# D18 O CMOS 5
V
PU10k to 5
V
Reset out
p
ut to IDE device
,
active low.
IDE
_
IR
Q
D12 I CMOS 3.3V
/
5
V
PD 10
K
Interru
p
t re
q
uest from IDE device.
IDE_CBLID# D77 I CMOS 3.3V / 5V PD 10K Input from off-Module hardware indicating the type of IDE cable being
used. High indicates a 40-pin cable used for legacy IDE modes. Low
indicates that an 80-pin cable with interleaved grounds is used. Such a
cable is required for Ultra-DMA 66, 100 and 133 modes.
IDE Signals Descriptions
I/O CMOS 3.3V / 5V Bidirectional data to / from IDE device.
O CMOS 3.3V / 3.3V Address lines to IDE device.