Specifications

dLAN 200 AVmodule 6400
11
devolo AG
Charlottenburger Allee 60 Tel.: [phone] www.devolo.com
D-52068 Aachen Fax: [phone] [e-mail]
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MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII Transmit Data. The MAC core drives
MII_TXD[3:0] and the PHY controller receives
MII_TXD[3:0]. MII_TXD[3:0] transitions
synchronously with respect to MII_TXCLK. For
each MII_TXCLK period in which MII_TXEN is
asserted, MII_TXD[3:0] is valid. MII_TXD0 is
the least-significant bit. The PHY controller
ignores MII_TXD[3:0] in isolate mode.
O I
21 MII_TXCLK MII Transmit Clock. MII_TXCLK is a
continuous clock that provides a timing
reference for the transfer of the MII_TXEN and
MII_TXD[3:0]
signals from the MAC core to the
PHY controller. The PHY controller sources
MII_TXCLK. The operating frequency of
MII_TXCLK is 25 MHz when operating at 100
Mbps and 2.5 MHz when operating at 10
Mbps. The PHY controller tri-states
MII_TXCLK in isolate mode.
I O
22 MII_TXEN MII Transmit Enable. A high assertion on
MII_TXEN indicates that the MAC core is
presenting nibbles to the PHY controller for
transmission. The INT6000 MAC core asserts
MII_TXEN with the first nibble of the preamble
and keeps MII_TXE
N asserted while all nibbles
to be transmitted are presented to the MII.
MII_TXEN is deactivated prior to the first
MII_TXCLK following the final nibble of the
frame. MII_TXEN transitions synchronously
with respect to MII_TXCLK.
The PHY controller
ignores MII_TXEN in isolate mode.
O I
16 MII_CRS MII Carrier Sense. The PHY controller asserts
MII_CRS when either transmit or receive
medium is non-idle. The PHY deasserts
MII_CRS when both transmit and receive
medium are idle. The PHY must ensure that
MII_CRS remains asserted throughout the
duration of a collision condition.
The transitions
on the CRS signal are not synchronous to
either the MII_TXCLK or the MII_RXCLK. The
PHY controller tri-states MII_CRS in isolate
mode.
I O
31 MII_MDIO MII Management Data In/Out. This is the data
input signal from the PHY controller. The PHY
drives the Read Data synchronously with
respect to the MII_MDCLK clock during the
read cycles. This is also the data output signal
from the MAC core that drives the control
information
during the Read/Write cycles to the
PHY controller. The MAC core drives the
MII_MDCLK signal
I/O I/O
32 MII_MDCLK MII Management Data Clock. The MAC core
sources MDC as the timing reference for
transfer of information on the MII_MDIO
signals. MII_MDCLK signal has no maximum
high or low times. MII_MDCLK minimum high
and low times are 160 ns each, and the
O I