Parallax P2 Edge Module - Datasheet
Table Of Contents
- FEATURES
- HARDWARE
- Pin Descriptions
- Hardware Connections
- Minimal Connections
- External Crystal
- Reset Switch
- SPI Flash Boot Memory
- MicroSD Boot Memory
- Dual Boot Memory
- OPERATION
- SYSTEM ORGANIZATION
- Cogs
- Cog RAM
- Register RAM
- Lookup RAM
- Execution
- Hub
- Hub RAM
- Cog-to-Hub RAM Interface
- System Clock
- CORDIC Solver
- Smart I/O Pins
- Pin Modes
- I/O Pin Circuit
- Equivalent Schematics
- Smart Modes
- PASM2 LANGUAGE IN BRIEF
- Math and Logic
- Pin & Smart Pin
- Branch
- Hub Control, FIFO, & RAM
- Event
- Interrupt
- Register Indirection
- CORDIC Solver
- Color Space Converter and Pixel Mixer
- Lookup Table, Streamer, and Misc
- SYSTEM CHARACTERISTICS
- Absolute Maximum Electrical Ratings
- DC Characteristics
- AC Characteristics
- PACKAGING
- CHANGE LOG
- PARALLAX INCORPORATED
Pin DIR/OUT Control (%TT)
Default = %00
for odd pins
'OTHER' = even pin's NOT output state (diff source)
for even pins
'OTHER' = unique pseudo-random bit (noise source)
for all pins
'SMART' = smart pin output which overrides OUT/OTHER
'DAC_MODE' is enabled when P[12:10] = %101
'BIT_DAC' outputs {2{P[7:4]}} for 'high' or {2{P[3:0]}} for 'low' in DAC_MODE
for smart pin mode off (%MMMMM = %00000)
DIR enables output
for non-DAC_MODE
0x
OUT drives output
1x
OTHER drives output
for DAC_MODE
00
OUT enables DAC, P[7:0] sets DAC level
01
OUT enables ADC, P[3:0] selects cog DAC channel
10
OUT drives BIT_DAC
11
OTHER drives BIT_DAC
for all smart pin modes (%MMMMM > %00000)
x0
output disabled, regardless of DIR
x1
output enabled, regardless of DIR
for DAC smart pin modes (%MMMMM = %00001..%00011)
0x
OUT enables DAC in DAC_MODE, P[7:0] overridden
1x
OTHER enables DAC in DAC_MODE, P[7:0] overridden
for non-DAC smart pin modes (%MMMMM = %00100..%11111)
0x
SMART/OUT drives output or BIT_DAC if DAC_MODE
1x
SMART/OTHER drives output or BIT_DAC if DAC_MODE
Copyright © Parallax Inc. 2021/05/27 ▪ Parallax Propeller 2 (P2X8C4M64P) Datasheet ▪ Page 22