Parallax P2 Edge Module - Datasheet
Table Of Contents
- FEATURES
- HARDWARE
- Pin Descriptions
- Hardware Connections
- Minimal Connections
- External Crystal
- Reset Switch
- SPI Flash Boot Memory
- MicroSD Boot Memory
- Dual Boot Memory
- OPERATION
- SYSTEM ORGANIZATION
- Cogs
- Cog RAM
- Register RAM
- Lookup RAM
- Execution
- Hub
- Hub RAM
- Cog-to-Hub RAM Interface
- System Clock
- CORDIC Solver
- Smart I/O Pins
- Pin Modes
- I/O Pin Circuit
- Equivalent Schematics
- Smart Modes
- PASM2 LANGUAGE IN BRIEF
- Math and Logic
- Pin & Smart Pin
- Branch
- Hub Control, FIFO, & RAM
- Event
- Interrupt
- Register Indirection
- CORDIC Solver
- Color Space Converter and Pixel Mixer
- Lookup Table, Streamer, and Misc
- SYSTEM CHARACTERISTICS
- Absolute Maximum Electrical Ratings
- DC Characteristics
- AC Characteristics
- PACKAGING
- CHANGE LOG
- PARALLAX INCORPORATED
PINA or PINB Input Selector
%AAAA
%BBBB
Selection
0xxx
true (default)
1xxx
inverted
x000
this pin's read state (default)
x001
relative +1 pin's read state
x010
relative +2 pin's read state
x011
relative +3 pin's read state
x100
this pin's OUT bit from cogs
x101
relative -3 pin's read state
x110
relative -2 pin's read state
x111
relative -1 pin's read state
PINA and PINB Logic/Filtering
%FFF
Logic/Filter
000
A, B (default)
001
A AND B, B
010
A OR B, B
011
A XOR B, B
100
A, B, both filtered using global filt0 settings
101
A, B, both filtered using global filt1 settings
110
A, B, both filtered using global filt2 settings
111
A, B, both filtered using global filt3 settings
The resultant 'A' will drive the IN signal in non-smart-pin modes.
Copyright © Parallax Inc. 2021/05/27 ▪ Parallax Propeller 2 (P2X8C4M64P) Datasheet ▪ Page 20