Parallax P2 Edge Module - Datasheet

Cogs can access Hub RAM either via the sequential FIFO interface, or by waiting for RAM slices of interest, while

yielding to the FIFO. If the FIFO is not busy (which is soon the case if data is not being read from or written to it)

random accesses will have full opportunity to access the composite Hub RAM.

There are three ways the hub FIFO interface can be used, and it can only be used for one of these at a time:

● Hub execution (when the PC is $00400..$FFFFF)

● Streamer usage (background transfers from Hub RAM → pins/DACs, or from pins/ADCs → Hub RAM)

● Software usage (fast sequential-reading or sequential-writing instructions)

For streamer or software usage, FIFO operation must be established by a RDFAST or WRFAST instruction

executed from Cog RAM (Register/Lookup, $00000..$003FF). After that, and while remaining in Cog RAM, the

streamer can be enabled to begin moving data in the background, or the two-clock RFxxxx/WFxxxx instructions

can be used to manually read and write sequential data.

The FIFO contains (#cogs+11) stages. When in read mode, the FIFO loads continuously whenever less than

(#cogs+7) stages are ﬁlled, after which point, up to 5 more longs may stream in, potentially ﬁlling all stages.

These metrics ensure that the FIFO never underﬂows, under all potential reading scenarios.