Documentation
Table Of Contents
IceBlip iCE40 LP1K module
The FPGA (A Lattice ICE40LP1K-CM36) is internally connected to the GD25Q20 2Mbit (256KB)
Flash and the PIC16F15325 CPU. Additionally an 8MHz clk form the CPU is available to the FPGA
.
Signal FPGA CPU
SS D5 RC3
SDI (SDO on Flash) F5 RC2
SDO (SDI on Flash) E4 RC1
SCK E5 RC4
SysClk (8MHz) F2 GBIN5 RA4
The iceBlip module is powered from an external 3.3v supply. There is an on-board 1.2v
regulator for the FPGA. All PIC and FPGA I/O pins are 3.3v, do not connect these to 5v devices.
IceBlip is programmed using iceBliprog. Linux and Windows programming software and source
code, is available at from www.robot-electronics.co.uk.
Any toolchain which generates a binary bit stream may be used, such as lattice iCEcube2.
Linux users also have the icestorm tools with yosys and nextpnr.
http://www.cli>ord.at/icestorm/