System information

Memory Maps
Memory Maps B-519
Table B-21 CSC/4 Memory Map
20B0000–20BFFFF Multibus NVRAM
(CSC/2, CSC/3,
CSC/4 cards)
Cards with 32 KB RAM only go through
0x20B7FFF.
2040000–20405FF CSC-16 card asynchronous
lines (CSC/2, CSC/3,
CSC/4 cards)
Each UART
1
is 0x20 bytes; there are two lines per
UART.
2010000–20AFFFF Shared memory on
CSC-R16 cards
Units 0–4. Each card has 0x20000 bytes of memory.
2000000–2007FFF Shared Multibus memory
primarily used by CSC-R
Token Ring cards
Each card has a system control area within this
memory, but the address of each area is decided at
runtime and is difficult to predict.
— System ROM address
space
The ROM monitor starts at the bottom of ROM and
is followed by the system image. The location of the
system image is not always known and is important
only for images that are run from ROM.
A bus error in valid ROM space might indicate bad
ROMs, a bad processor card, or in the case of
run-from-ROM images, a software bug in which the
software tries to write into ROM.
1000000–107FFFF System ROM address
space
512-KB system ROMs on the CSC/2, CSC/3, and
CSC/4 cards, IGS, CS-3000. Run from ROM, system
images exist only on the CSC/2 card.
1000000–10FFFFF System ROM address
space
1-MB system ROMs on the CSC/2, CSC/3, and
CSC/4 cards, IGS, CS-3000. Run from ROM, system
images exist only on the CSC/2 card.
1000000–11FFFFF System ROM address
space
2-MB system ROMs on the CSC/2, CSC/3, and
CSC/4 cards and the IGS. Run from ROM, system
images exist only on the CSC/2 card.
— Main processor RAM Bus errors here are usually caused by a hardware
failure on the processor card.
0000–0FFFFF Main processor RAM CSC/2 card and IGS with 1 MB. On the IGS, the top
0.5 MB is shared packet memory.
0000–17FFFF Main processor RAM IGS with 1.5 MB. The top 0.5 MB is shared packet
memory.
0000–3FFFFF Main processor RAM CSC/3 card
0000–FFFFFF Main processor RAM CSC/4 card
0000–47FFFF Main processor RAM IGS with 4.5 MB. The top 0.5 MB is shared packet
memory.
0000–0FFF System page The system page contains several processor and
ROM monitor data structures, primarily the trap and
interrupt vectors. If the low page gets corrupted, the
system might hang rather than crash.
1 UART = Universal Asynchronous Receiver/Transmitter
Address Description Comments