User Guide

141
Pin PinName Symbol I/O Type Det
Op
(Int.)
Pu/Pd
(Ext.)
Res P.OFF
PURE
D
CEC
STBY
Q.STBY
CEC+
QSTBY
Function
88 P106/(AN6)
DSPPWR/
SubnCONFIG
O/O C - - - Z Z O/L O/L O/L O/L
DSP control pin (ADSP-21367-333) /FPGA rewriting (For
GUI FPGA: NCONF)
89 P105/(AN5)
DSP ROMRST/
SUBnCE
O/O C - - - Z Z O/L O/L O/L O/L
Rewriting memory reset (Reset : L)/FPGA rewriting control
(For GUI FPGA: CE)
90 P104/(AN4) NC O - Lv - SCPU3VPu Z Z - - - - Non
91 P103/(AN3)
DSPFLAG0/
SUBDATA_O
I/O - Lv - Pd Z Z - - - -
DSP control pin (ADSP-21367-333): Conrming the
operation/FPGA rewriting control (For GUI FPGA: Data
light)
92 P102/(AN2)
DSP1ICS/
SUBnCS
O/O C - D3VPu Z Z O/L O/L O/L O/L
DSP control pin (ADSP-21367-333): Communicating
enable/FPGA rewriting control (For GUI FPGA: CS)
93 P101/(AN1)
DSPFLAG1/
SUBASDI
I/O C - D3VPu Z Z O/L O/L O/L O/L
DSP control pin (ADSP-21367-333) /FPGA rewriting
control (For GUI FPGA: Communication response)
94 AVSS AVSS - - - - - - - - - - - AD GND
95 P100/(AN0) VSEL CLK O C - - - Z Z O/L O/L O/L O/L GUI built-in VIDEO SW cotrol pin
96 VREF VREF - - - - - - - - - - - AD 3.3 standard +V
97 AVCC AVCC - - - - - - - - - - - AD +3.3V
98 P97/(SIN4) Tx EN O C - - - Z Z O/L - - - AD8195 ENABLE pin for Front HDMI control
99 P96/(SOUT4)
(DSP2ICS)/
SCONF_DONE
(O)/I - - - Pd Z Z O/L O/L O/L O/L
Reserve (DSP1 control pin (ADSP-21367-333):
Communicate enable)/FPGA rewriting control (For GUI
FPGA: ASDI)
100 P95/(CLK4) NC O C - - - Z Z O/L O/L O/L O/L Non