User Guide

65
S-302
NT5DS16M16CS (IC202: 1U-3809)
Input/Output Functional Description
Symbol Type Function
CK, CK
Input
Clock: CK and CK
are differential clock inputs. All address and control input signals are sampled
on the cross ing of the positive edge of CK and negative edge of CK
. Output (read) data is refer-
enced to the crossings of CK and CK
(both directions of crossing).
CKE Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. T a king CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for s elf refresh entry. CKE is asynchronous for self
refresh exit. CK E must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK
and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin.
CS
Input
Chip Select: A ll commands are masked when CS
is registered high. CS provides for external
bank selection on systems with multiple banks. CS
is considered part of the command code. The
standard pinout includes one CS
pin.
RAS
,CAS,WE Input Command Inputs: RAS,CASand WE (along with CS) define the command being entered.
DM Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write acces s. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
BA0, BA1 Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write o r Precharge
command is being applied. BA0 and BA1 also det ermines if the mode reg ister or extended mode
register is to be accessed during a MRS or EMRS cycle.
A0 - A12 Input
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether th e Pre-
charge applies to one bank (A 10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA 0, BA1. The address inputs also provide the op-code during a Mode
Register Set com mand.
DQ Input/Output Data Input/Output: Data bus.
DQS, LDQS, UDQS Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data. For the x16, LDQS corresponds to the dat a on DQ0-
DQ7; UDQS corresponds to the data on DQ8-DQ15
NC No Connect: No internal electrical connection is present.
NU Electrical connection is present. Should not be connected at second level of assembly.
V
DDQ
Supply DQ Power Supply: 2.5V ± 0.2V for DDR333; 2.6V ± 0.1V for DDR400.
V
SSQ
Supply DQ Ground
V
DD
Supply Power Supply: 2.5V ± 0.2V for DDR333; 2.6V ± 0.1V for DDR400.
V
SS
Supply Ground
V
REF
Supply SSTL_2 reference voltage