User Guide

63
S-302
IC302 expansion output (BU2090)
90 P25 DSP_IO_MUTE O DSP IO MUTE control output (DSO IO MUTE: H)
91 P24 _AD/DIG O AD way/DIGITAL switching (AD way:L)
92 P23 _ERR_MUTE O Mute output at time of DSP ERR occurrence (MUTE:L)
93 P22 _BSE O Bit Stream Enable(Bit Stream:L)
94 P21 TDO_VFPGA I Main PLD JTAG data input
95 P20 COMP_DET I Component video input detection
96 P17/INT5 TMS_AV O Main PLD JTAG clock output
97 P16/INT4 S_DET I S video input detection
98 P15/INT3 TDI_AV O Main PLD JTAG data output (S-302 schematic TDO_APLD inscription)
99 P14 VSEL_CLK O Video selector clock
100 P13 VSEL_DATA O Video selector data
101 P12 _COMP_MUTE2 O COMPONENT output last step driver (NJM2581) MUTE signal (MUTE:L)
102 P11 _S/V_MUTE O YC/CVBS output MUTE signal (MUTE: L)
103 P10 nCONFIG O VIDEO PLD control terminal
104 P07/AN07 nCS O VIDEO PLD control terminal
105 P06/AN06 nDE O VIDEO PLD control terminal
106 P05/AN05 DDCLK O VIDEO PLD control terminal
107 P04/AN04 DATA_0 O VIDEO PLD control terminal
108 P03/AN03 ASDI O VIDEO PLD control terminal
109 P02/AN02 _DIR_RST O DIR reset output Reset:L
110 P01/AN01 DIR_CE O DIR chip enabling
111 P00/AN00 DIR/CODEC_CK O DIR/CODEC clock output
112 P117 DIR_MISO I Data input from DIR
113 P116 DIR/CODEC_MOSI O Data output to DIR/CODEC
114 P115 _DSPROM_RST O ROM reset for DSP
115 P114 _DSP_RST O Reset for DSP (Reset:L)
116 P113 DSP_CS O DSP chip select
117 P112 FLAG0 I DSP FLAG0 input
118 P111 N.C. O OPEN
119 P110 N.C. O OPEN
120 P107/AN7 Pull up O OPEN
121 P106/AN6 Pull up O OPEN
122 P105/AN5 Pull up O OPEN
123 P104/AN4 Pull up O OPEN
124 P103/AN3 Pull up O OPEN
125 P102/AN2 Pull up O OPEN
126 P101/AN1 Pull up O OPEN
127 AVSS AVSS - AD GND
128 P100/AN0 CONF_DONE O VIDEO PLD control terminal
Port Port name I/O
Q0 SIN_SELA O
Q1 SIN_SELB O
Q2 SIN_SELC O
Q3 VIN_SELA O
Q4 VIN_SELB O
Q5 VMONI_SEL O
Q6 N.C. O
Q7 N.C. O
Q8 _COMP MUTE1 O
Q9 FIL_SEL O
Q10 N.C. O
Q11 SMONI_SEL O
Pin No Port name Function I/O Explanation