User Guide

62
S-302
23 P84/INT2 _DIR_INT I DIR interrupt input
24 P83/INT1 SUB_ACK I
MAIN-SUB uCom communications control input terminal (ACK “L” return from main uCom)
25 P82/INT0 N.C. O OPEN
26 P81/TA4IN N.C. O OPEN
27 P80 PWB_CHK O PWB check
28 P77 _DEC_RST O Reset for ADV7403
29 P76 _ENC2_RST O Reset for ADV7320-2
30 P75/TA2IN N.C. OPEN
31 P74/TA2OUT N.C. OPEN
32 P73/CTS2/TA1IN N.C. OPEN
33 P72/CLK2 N.C. O OPEN
34 P71/RXD2 N.C. O OPEN
35 P70/TXD2 N.C. O OPEN
36 P67/TXD1 F_TXD2 O
Data output for Flash rewriting /HDMI DEBUG 5 (DEBUG output for communication)
37 VCC1 VCC1 - +3.3V
38 P66/RXD1 F_RXD2 O
Data output for Flash rewriting /HDMI DEBUG 4 (DEBUG output for communication)
39 VSS VSS - GND
40 P65/CLK1 N.C. O OPEN
41 P64/CTS1 N.C. O OPEN
42 P63/TXD0 SUB_STXD O Data output to of main uCom
43 P62/RXD0 SUB_SRXD I Data input to of main uCom
44 P61/CLK0 SUB_CLK I Clock input from of main uCom
45 P60/CTS0 SUB_REQ O Communication Request to of main uCom
46 P137 CK_SEL O Video Encoder clock switching for ZONE2
47 P136 HD/_SD O VideoEncoder resolution switching(SD/SD or more)
48 P135 HDMI_DEBUG_3 O HDMI DEBUG 3 (DEBUG output)
49 P134 HDMI_DEBUG_6 O HDMI DEBUG 6 (DEBUG output)
50 P57 _ENC1_RST O Reset for ADV7320-1
51 P56 V_DET I CVBS video input detection
52 P55/EPM F_EPM2 O Port for Flash rewriting/HDMI DEBUG 2 (DEBUG output)
53 P54 N.C. O OPEN
54 P133 N.C. O OPEN
55 P132 HDMI_SCL I/O VIDEO I2C clock (HDMI system)
56 P131 HDMI_SDA I/O VIDEO I2C data (HDMI system)
57 P130 VD_SCL I/O VIDEO I2C clock (Video processing system)
58 P53 VD_SDA I/O VIDEO I2C data (Video processing system)
59 P52 N.C. O OPEN
60 P51 N.C. O OPEN
61 P50/CE _F_CE2 O Port for Flash rewriting/HDMI DEBUG 1 (DEBUG output)
62 P127 P_SAVE O
COMPONENT → CONVERT route DISABLE terminal
63 P126 N.C. O OPEN
64 P125 N.C. O OPEN
65 P47 N.C. O OPEN
66 P46 N.C. O OPEN
67 P45 FNVL_DA O Function volume IC data output (RENESAS system data)
68 P44 FNVL_CK O Function volume IC clock output (RENESAS system clock)
69 P43 FNVL_CE O Function volume IC latch output (RENESAS system latch )
70 P42 N.C. O OPEN
71 P41 N.C. O OPEN
72 P40 N.C. O OPEN
73 P37 N.C. O OPEN
74 P36 N.C. O OPEN
75 P35 N.C. O OPEN
76 P34 EXT_CK O Video system (+5V system) expansion output port clock output
77 P33 EXT_DA O Video system (+5V system) expansion output port clock output
78 P32 CODEC_MISO I Data input from CODEC
79 P31 HDMI SENS I HDMI IN signal presence detection input
80 P124 VSEL_CS1 O Video selector PLD chip select
81 P123 VSEL_CS2 O Video selector FPGA chip select
82 P122 CODEC_RST O CODEC reset output
83 P121 PRE_MUTE_SUB O Mute output of volume output
84 P120 HP_MUTE_SUB O MUTE output of head phone MUTE:H
85 VCC2 VCC2 - +3.3V
86 P30 BE/_DIR O Route of voice output (BE/external input) switching
87 VSS VSS - GND
88 P27 CODEC_CE O ODEC chip enabling
89 P26 TCK_AV O Main PLD JTAG
Pin No Port name Function I/O Explanation