User Guide
45
S-301
HY57V6432320DTP (IC404: 1U-3692)
VDD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
N.C
V
DD
DQM0
WE
CAS
RAS
CS
N.C
BA0
BA1
A10/AP
A0
A1
A2
DQM2
V
DD
N.C
DQ16
V
SSQ
DQ17
DQ18
V
DDQ
DQ19
DQ20
V
SSQ
DQ21
DQ22
V
DDQ
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
N.C
V
SS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
N.C
DQ31
V
DDQ
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DDQ
DQ26
DQ25
V
SSQ
DQ24
V
SS
PIN CONFIGURATION
BLOCK DIAGRAM
Bank Select
Data Input Register
512K x 32
512K x 32
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
RAS CAS WE DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
512K x 32
512K x 32
Timing Register
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
A
0 ~ A10 Address
Row/column addresses are multiplexed on the same pins.
Row address : RA
0 ~ RA10, Column address : CA0 ~ CA7
BA0,1 Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS
low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS
low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS
,WE active.
DQM0 ~ 3 Data input/output mask
Makes data output Hi-Z, t
SHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ
0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins.
V
DD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
V
DDQ/VSSQ Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
NC No Connection This pin is recommended to be left No connection on the device.