User Guide

20
S-301
ADVSS 112 G Analog ground for video DAC.
YUV5
113
O YUV pixel 5 output data.
YDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV6
114
O YUV pixel 6 output data.
VDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV7
115
O YUV pixel 7 output data.
FDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
CAMIN3 I Camera YUV 3.
PCLK2XSCN
116
I/O 27-MHz video output pixel clock.
CAMIN4 I Camera YUV 4.
PCLKQSCN
117
O 13.5-MHz video output pixel clock.
CAMIN5 I Camera YUV 5.
AUX3[2] I/O Aux3 data I/O.
VSYNC#
118
I/O Vertical sync (active-low).
CAMIN6 I Camera YUV 6.
AUX3[1] I/O Aux3 data I/O.
HSYNC#
119
I/O Horizontal sync (active-low).
CAMIN7 I Camera YUV 7.
AUX3[0] I/O Aux3 data I/O.
HD[5:0]
122:127
I/O Host data bus lines 5:0.
DCI[5:0] I/O DVD channel data I/O.
AUX1[5:0] I/O Aux1 data I/O.
HD6
128
I/O Host data bus line 6.
DCI6 I/O DVD channel data I/O.
AUX1[6] I/O Aux1 data I/O.
VFD_DOUT I VFD data output.
HD7
131
I/O Host data bus line 7.
DCI7 I/O DVD channel data I/O.
AUX1[7] I/O Aux1 data I/O.
VFD_DIN I VFD data input.
HD8
132
I/O Host data bus line 8.
DCI_FDS# I/O DVD input sector start (active-low).
AUX2[0] I/O Aux2 data I/O.
VFD_CLK I VFD clock input.
p( )
Name Pin Numbers I/O Definition