User Guide

14
14
DN-X1500
AK4103A (IC502)
Block Diagram
AK4103A PIN/FUNCTION
6
5
4
3
2
1V1
TRANS
MCLK
PDN
SDTI
BICK
LRCK 7
FS0/CSN 8
U1
DIF2
DIF1
DIF0
TXP
TXN
VSS
VDD
Top
View
10
9FS1/CDTI
FS2/CCLK
FS3/CDTO 11
C1 12
CKS1
CKS0
BLS
ANS
19
20
21
22
23
24
18
17
15
16
14
13
Host Serial
Interface
Audio Serial
Interface
BICK
LRCK
SDTI
TXP
MUX
CRCC Generator
Prescaler
RS422 Line Driver
Biphase
Encoder
DIF2 DIF1 DIF0 CKS1 CKS0 MCLK BLS TRANS VSS VDD
TXN
C1
U1
V1
FS0
FS1
FS2
FS3
Register
CSN
CCL
K
CDT
I
CDT
O
ANS
PDN
No. Pin Name I/O Description
1 V1 I Validity Bit Input Pin
2 TRANS I Audio Routing Mode (Transparent Mode) Pin at Synchronous mode
0: Normal mode, 1: Audio routing mode (transparent mode)
3 PDN I Power Down & Reset Pin (Pull-up Pin)
When “L”, the AK4103A is powered-down, TXP/N pins are “L” and the
control registers are reset to default values.
4 MCLK I Master Clock Input Pin
5 SDTI I Audio Serial Data Input Pin
6 BICK I/O Audio Serial Data Clock Input/Output Pin
Serial Clock for SDTI pin which can be configured as an output based on
the DIF2-0 inputs.
7 LRCK I/O Input/Output Channel Clock Pin
Indicates left or right channel, and can be configured as an output based on
the DIF2-0 inputs.
FS0 I Sampling Frequency Select 0 Pin at Synchronous mode (Pull-down Pin)
CSN I Host Interface Chip Select Pin at Asynchronous mode (Pull-down Pin)
8
AKMODE I AK4112B Mode Pin at Audio routing mode (Pull-down Pin)
0: Non-AKM receivers mode, 1: AK4112B mode
FS1 I Sampling Frequency Select 1 Pin at Synchronous mode (Pull-down Pin)9
CDTI I Host Interface Data Input Pin at Asynchronous mode (Pull-down Pin)
FS2 I Sampling Frequency Select 2 Pin at Synchronous mode (Pull-down Pin)10
CCLK I Host Interface Bit Clock Input Pin at Asynchronous mode (Pull-down Pin)
FS3 I Sampling Frequency Select 3 Pin at Synchronous mode (Pull-down Pin)11
CDTO O Host Interface Data Output Pin at Asynchronous mode (Pull-down Pin)
12 C1 I Channel Status Bit Input Pin
13 ANS I Asynchronous/Synchronous Mode Select Pin (Pull-up Pin)
0: Asynchronous mode, 1: Synchronous mode
14 BLS I/O Block Start Input/Output Pin (Pull-down Pin)
In normal mode, the channel status block output is “H” for the first four
bytes. In audio routing mode, the pin is configured as an input. When PDN
pin = “L”, BLS pin goes “H” at Normal mode.
15 CKS0 I Clock Mode Select 0 Pin (Pull-up Pin)
16 CKS1 I Clock Mode Select 1 Pin (Pull-down Pin)
17 VDD -
Power Supply Pin, 4.75V
∼
5.25V
18 VSS - Ground Pin, 0V
19 TXN O Negative Differential Output Pin
20 TXP O Positive Differential Output Pin
21 DIF0 I Audio Serial Interface Select 0 Pin (Pull-down Pin)
22 DIF1 I Audio Serial Interface Select 1 Pin (Pull-down Pin)
23 DIF2 I Audio Serial Interface Select 2 Pin (Pull-down Pin)
24 U1 I User Data Bit Input Pin for Channel 1 (Pull-down Pin)
Notes:
1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43k
Ω
(typ).
2. All input pins except internal pull-down/pull-up pins should not be left floating.