User Guide

35
DN-S700
K4S641632D Block diagram
M29W800DB (U3)
Bank Select
Data Input Register
1M x 16
1M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
1M x 16
1M x 16
Timing Register