User Guide

27
27DN-S3000
TMP86CM47U-3RD2 (DS: IC151)
TMP86CM47U-3RD2 Terminal Function
FunctionI/O
Pin
No.
Pin Name Symbol DET Ext Ini Res
1 VSS VSS GND (0V)
2 XIN XIN I Oscillation input 8.0MHz
3 XOUT XOUT O Oscillation output
4 TEST TEST I Fixed to L
5 VDD VDD Power (+3.3V)
6 P21(LED) DVSEL O Pu L H Not used
7 P22 BREQ1_ O Pu H H System µcom bus request
8 RESET_ RST_ I µcom reset
9 P20 DRLCH O Pu H H ATAPI data register latch signal, H: Latch
10 P00(INT0) MCMD_ I System µcom serial interface
11 P01 DMA O Pu L H ATAPI DMA mode select (H: DMA)
12 P02 DMABSY1 I Pu H In DMA flag (L: DMA data transfer)
13 P03 ATANS O Pu H H System µcom serial interface
14 P04(SO) ATDATA O Pu H H System µcom serial data receive signal
15 P05(SI) MDATA I System µcom serial data send signal
16 P06(SCK_) MCLK I System µcom serial send/receive clock
17 P07(INT4/LED) BSYIN_ I H TXD BUSY input
18 P17 BSYOUT_ O Pu H H TXD BUSY output signal (L: BUSY)
19 P16 DRES_ O Pd L L DSP reset (L: Reset)
20 P15 DMAR_/W I/O Pu/Pd H L/H ATAPI DMA direction select (L: Read) *
21 P14 RD_ O H ATAPI read strobe
22 P13 WR_ O H ATAPI write strobe
23 P12(INT2) INTRQ I Lv ATAPI interrupt request signal
24 P11(INT1) DMARQ I Lv Pd ATAPI DMA request signal (Pd with 5.6kW)
25 P10 IORDY I Pu H
ATAPI data transfer cycle extend request signal (Pu with 1.0kW)
26 P30 D0 I/O Pd L L ATAPI data bus 0 (APRES_ATAPI reset)
27 P31 D1 I/O ATAPI data bus 1 (CS1 device register chip select 1)
28 P32 D2 I/O ATAPI data bus 2 (CS0 device register chip select 0)
29 P33 D3 I/O ATAPI data bus 3 (DA2 device register select 2)
30 P34 D4 I/O ATAPI data bus 4 (DA1 device register select 1)
31 P35 D5 I/O ATAPI data bus 5 (DA0 device register select 0)
32 P36 D6 I/O ATAPI data bus 6
33 P37 D7 I/O ATAPI data bus 7
34 VAREF VAREF I
GND (0V), Analog ref. V for A/D conversion, A/D not used
35 AVDD AVDD I Power (+3.3V), Power for A/D conversion circuit only
36 AVSS AVSS I GND (0V), Analog GND for A/D conversion
37 P40 D8 I/O ATAPI data bus 8
38 P41 D9 I/O ATAPI data bus 9
39 P42 D10 I/O ATAPI data bus 10
40 P43 D11 I/O ATAPI data bus 11
41 P44 D12 I/O ATAPI data bus 12
42 P45 D13 I/O ATAPI data bus 13
43 P46 D14 I/O ATAPI data bus 14
44 P47 D15 I/O ATAPI data bus 15
1
11
12
22
23
33
34
44
TOP VIEW
* Pd or Pu detected in input port when power on, Pd=CD1, Pu=CD2