User Guide

25
DHT-500SD
PCM1754(DSP:IC55)
PIN ASSIGNMENTS
SCK
FMT
MUTE
DEMP
TEST
ZEROA
V
COM
AGND
16
15
14
13
12
11
10
9
BCK
DATA
LRCK
DGND
NC
V
CC
V
OUT
L
V
OUT
R
PCM1754
(TOP VIEW)
1
2
3
4
5
6
7
8
FUNCTIONAL BLOCK DIAGRAM
Power Supply
DGND
Enhanced
Multi-Level
Delta-Sigma
Modulator
V
OUT
L
4ı /8ı
Oversampling
Digital
Filter
and
Function
Control
Audio
Serial
Port
BCK
LRCK
DATA
Serial
Control
Port
Zero Detect
(TEST)
SCK
System
Clock
Manager
(MUTE) MC
(FMT) ML
Output Amp
and
Low-Pass Filter
(DEMP) MD
DAC
V
COM
System Clock
AGND
V
CC
ZEROR/ZEROA
†
(ZEROA)
ZEROL/NA
†
Output Amp
and
Low-Pass Filter
DAC
V
OUT
R
†
Open-Drain Output for the PCM1755
( ): PCM1754