User Guide
21
DHT-500SD
ST92F150CVT1(MAIN:IC11)
Pin Configuration (Top-view TQFP100)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
ST92F150CVT1
(MAIN:IC11)
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
NC
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
V
DD
V
SS
P0.6/A6/D6
P0.5/A5/D5
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
P0.4/A4/D4
P1.7/A15
A20/P9.6
TX0/WAIT
/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
TXCLK/CLKOUT/P5.4
OCMPA1/P4.2
V
DD
A21/P9.7
WDIN/SOUT/P5.3
DCD/WKUP8/P5.6
V
SS
ICAPB1/OCMPB1/P4.3
SDA/P4.6
SIN/WKUP2/P5.2
RXCLK/WKUP7/P5.5
CLOCK2/P4.1
EXTCLK1/WKUP4/P4.4
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
WKUP9/RTS/P5.7
ICAPA1/P4.0
EXTRG/STOUT/P4.5
WKUP1/SCL/P4.7
OCMPB0/P3.3
EXTCLK0/SS
/P3.4
MISO/P3.5
P9.5/A19
P9.4/A18
P9.2/A16
HW0SW1
P7.7/AIN15/7/WKUP13
P7.4/AIN12/WKUP3
P9.3/A17
P9.0/RDI
RESET
P7.6/AIN14/WKUP12
P7.5/AIN13/WKUP11
P7.1/AIN9
P9.1/TDO
OSCIN
V
SS
P7.3/AIN11
P7.0/AIN8/CK_AF
P8.7/AIN7
OSCOUT
V
DD
P7.2/AIN10
AV
SS
AV
DD
P8.6/AIN6
P8.5/AIN5
MOSI/P3.6
SCK/WKUP0/P3.7
RW
TOUTA0/P2.2
V
SS
*V
TEST
V
REG
TINPB0/P2.1
TOUTB0/P2.3
V
DD
V
REG
A10/P1.2
TINPA0/P2.0
TINPB1/P2.5
TOUTB1/P2.7
A8/P1.0
A11/P1.3
A12/P1.4
TINPA1/P2.4
TOUTA1/P2.6
A9/P1.1
WKUP6
NC
A13/P1.5
A14/P1.6
*V
TEST
must be kept low in standard operating mode.
Architectural Block Diagram
256 bytes
Register File
RAM
2/4 Kbytes
ST9 CORE
8/16 bits
CPU
Interrupt
Management
MEMORY BUS
RCCU
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Ports
1,9*
REGISTER BUS
WATCHDOG
AS
DS
RW
WAIT
NMI
DS2
RW*
MISO
MOSI
SCK
SS
A[10:8]
A[21:11]*
A[7:0]
D[7:0]
ST. TIMER
SPI
SDA
SCL
I
2
CBUS
FLASH
128/64 Kbytes
WDOUT
HW0SW1
STOUT
* Not available on 64-pin version.
Fully
Prog.
I/Os
P0[7:0]
P1[7:3]*
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]*
P4[7:4]
P4[3:0]*
P5[7:0]
P6[5:2,0]
P6.1*
P7[7:0]
P8[7:0]*
P9[7:0]*
MF TIMER 0
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
INT[5:0]
INT6*
WKUP[13:0]
WKUP[15:14]*
MF TIMER 1
E
3TM
1Kbyte
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
ADC
AV
DD
AV
SS
AIN[15:8]
AIN[7:0]*
EXTRG
RX0
TX0
CAN_0
V
REG
VOLTAGE
REGULATOR
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8* and Port9*.
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
EF TIMER 0 *
EF TIMER 1 *
SCI M
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
SCI A*
RDI
TDO