User Guide

27
ADV-700
Pin Name FunctionPin No. I/O
36 NC 
37 NC 
38 VSS  GND pin
39 BA7 O Buffer address output
40 BA6 O Buffer address output
41 BA5 O Buffer address output
42 BA4 O Buffer address output
43 BA0 O Buffer address output
44 VSS  GND pin
45 BA2 O GND pin
46 BA1 O GND pin
47 BA3 O Buffer address output
48 TEST0 I Test pin, Fixed to L
49 TEST1 I Test pin, Fixed to L
50 TEST2 I Test pin, Fixed to L
51 VSSck GND pin (for clock system)
52 XI I Master clock in/output, feedback R built-in
53 XO O Master clock in/output, feedback R built-in
54 VDDck Power pin (for clock system)
55 DIGO O Digital out pin
56 NC 
57 PDCK I Data read clock input
58 PDRQN I Data effective flag input
59 PSYCN I Sync signal input
60 PDA8 I Parallel data 8 input
61 PDA7 I Parallel data 7 input
62 PDA6 I Parallel data 6 input
63 PDA5 I Parallel data 5 input
64 VSS  GND pin
65 PDA4 I Parallel data 4 input
66 PDA3 I Parallel data 3 input
67 PDA2 I Parallel data 2 input
68 PDA1 I Parallel data 1 input
69 PDA0 I Parallel data 0 input
70 VSS  GND pin
71 NC 
72 NC 
73 NC 
74 AZCK I Ref. clock input for audio playback
75 ABCK O Bit clock (BCK) output for audio playback
76 ADO O Data output for audio playback
77 ACHCK O Channel clock (LRCK) output for audio playback
78 VDD  Power pin
79 SEDVD I Input IF select
80 VSS  GND pin
81 MD0 I/O µcom data in/output, tri-state output
82 MD1 I/O µcom data in/output, tri-state output
83 MD2 I/O µcom data in/output, tri-state output
84 MD3 I/O µcom data in/output, tri-state output
85 MD4 I/O µcom data in/output, tri-state output
86 MD5 I/O µcom data in/output, tri-state output
87 MD6 I/O µcom data in/output, tri-state output
88 MD7 I/O µcom data in/output, tri-state output
89 VSS  GND pin
90 VDD  Power pin
91 MA0 I µcom address input
92 MA1 I µcom address input
93 MA2 I µcom address input
94 MA3 I µcom address input