User Guide

21
ADV-700
Pin Name
FunctionPin No.
I/O
Pin Name
FunctionPin No.
I/O
56 DMA 3 O DRAM address bus
57 DMA 4 O DRAM address bus
58 DMA 5 O DRAM address bus
59 Vcc I 3.6V power supply
60 Vss I GND
61 DMA 6 O DRAM address bus
62 DMA 7 O DRAM address bus
63 DMA 8 O DRAM address bus
64 DMA 9 O DRAM address bus
65 DMA 10 O DRAM address bus
66 DMA 11 O DRAM address bus
67 Vss I GND
68 Vcc I 3.6V power supply
69 DCAS# O Column address strobe, active low
70
DOE# O Output enable, active low
DSCK_EN I Clock enable, active low
71 DWE# O DRAM write enable, active low
72 DRAS 0# O Row address strobe, active low
73 DRAS 1# O Row address strobe, active low
74 DRAS 2# O Row address strobe, active low
75 Vcc I 3.6V power supply
76 Vss I GND
77 DB 0 I/O DRAM data bus
78 DB 1 I/O DRAM data bus
79 DB 2 I/O DRAM data bus
80 DB 3 I/O DRAM data bus
81 DB 4 I/O DRAM data bus
82 DB 5 I/O DRAM data bus
83 Vcc I 3.6V power supply
84 Vss I GND
85 DB 6 I/O DRAM data bus
86 DB 7 I/O DRAM data bus
87 DB 8 I/O DRAM data bus
88 DB 9 I/O DRAM data bus
89 DB 10 I/O DRAM data bus
90 DB 11 I/O DRAM data bus
91 Vss I GND
92 Vcc I 3.6V power supply
93 DB 12 I/O DRAM data bus
94 DB 13 I/O DRAM data bus
95 DB 14 I/O DRAM data bus
96 DB 15 I/O DRAM data bus
97 DCS 1# O SDRAM chip select [1], active low
98 Vss I GND
99 Vcc I 3.6V power supply
100 DCS 0# O SDRAM chip select [0], active low
101 DQM O Data input/output mask
102 DSCK O Clock to SDRAM
103 Vss I GND
104 Vcc I 3.6V power supply
105 DCLK I Clock input (27MHz)
106 YUV 0 O 8-bit YUV output
107 YUV 1 O 8-bit YUV output
108 YUV 2 O 8-bit YUV output
109 YUV 3 O 8-bit YUV output
110 YUV 4 O 8-bit YUV output
111 Vcc I 3.6V power supply
112 Vss I GND
113 YUV 5 O 8-bit YUV output
114 YUV 6 O 8-bit YUV output
115 YUV 7 O 8-bit YUV output
116 PCLK2XSCN I/O 2X pixel clock
117 PCLKQSCN I/O Pixel clock
118 VSYNCH# I/O
Vertical sync for screen video interface,
programmable for rising or falling edge,
active low
119 HSYNCH# I/O
Horizontal sync for screen video
interface, programmable for rising or
falling edge, active low
120 Vss I GND
121 Vcc I 3.6V power supply
122 HD 0 I/O Host data bus
123 HD 1 I/O Host data bus
124 HD 2 I/O Host data bus
125 HD 3 I/O Host data bus
126 HD 4 I/O Host data bus
127 HD 5 I/O Host data bus
128 HD 6 I/O Host data bus
129 Vss I GND
130 Vcc I 3.6V power supply
131 HD 7 I/O Host data bus
132 HD 8 I/O Host data bus
133 HD 9 I/O Host data bus
134 HD 10 I/O Host data bus
135 HD 11 I/O Host data bus
136 HD 12 I/O Host data bus
137 HD 13 I/O Host data bus
138 Vss I GND
139 Vcc I 3.6V power supply
140 HD 14 I/O Host data bus
141 HD 15 I/O Host data bus
142 HWRQ# O Host write request
143 HRDQ# O Host read request
144 HIRQ I/O Host interrupt
145 HRST# O Host reset
146 HIORDY I Host I/O ready
147 Vss I GND
148 Vcc I 3.6V power supply
149
HWR# O Host write request
HWR#/DCI_ACK# I, I
Host write / DCI interface acknowledge
signal, active low
150 HRD#/DCI_CLK I, I Host read / DCI interface clock
151 HIOCS16# I Device 16-bit data transfer
152 HCS1FX# O Host select 1
153 HCS3FX# O Host select 3
154 HA 0 I/O Host address bus
155 HA 1 I/O Host address bus