User Guide
20
ADV-700
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157
Vcc
LA4
LA5
LA6
LA7
LA8
LA9
Vss
Vcc
LA10
LA11
LA12
LA13
LA14
LA15
LA16
Vss
Vcc
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
Vss
Vcc
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL1
TSD/SEL_PLL0
Vss
Vcc
TSD1
TSD2
TSD3
MCLK
TBCK
SPDIF_DOBM
NC
Vss
Vcc
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
Vcc
Vss
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
Vcc
Vss
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
Vss
Vcc
DCAS#
DOE#/DSCK_EN
DWE#
DRAS0#
DRAS1#
DRAS2#
Vcc
Vss
DB0
DB1
DB2
DB3
DB4
DB5
Vcc
Vss
DB6
DB7
DB8
DB9
DB10
DB11
Vss
Vcc
DB12
DB13
DB14
DB15
DCS1#
Vss
Vcc
DCS0#
DQM
DSCK
Vss
Vcc
Vss
HA1
HA0
HCS3FX#
HCS1FX#
HIOCS16#
HRD#/DCI_ACK#
HWR#/DCI_CLK
Vcc
Vss
HIORDY
HRST#
HIRQ/DCI_ERR#
HRDQ#
HWRQ#/DCI_REQ#
HD15
HD14
Vcc
Vss
HD13
HD12
HD11
HD10
HD9
HD8/DCI_FDS#
HD7/DCI7
Vcc
Vss
HD6/DCI6
HD5/DCI5
HD4/DCI4
HD3/DCI3
HD2/DCI2
HD1/DCI1
HD0/DCI0
Vcc
Vss
HSYNCH#
VSYNCH#
PCLKQSCN
PCLK2XSCN
YUV7
YUV6
YUV5
Vss
Vcc
YUV4
YUV3
YUV2
YUV1
YUV0
DCLK
Vss
LA3
LA2
LA1
LA0
NC
NC
Vcc
Vss
LWRHL#
LWRLL#
LD15
LD14
LD13
LD12
Vcc
Vss
LD11
LD10
LD9
LD8
LD7
LD6
LD5
Vss
Vcc
LD4
LD3
LD2
LD1
LD0
Vss
LCS3#
LCS2#
LCS1#
LCS0#
Vcc
Vss
LOE#
AUX7
AUX6
AUX5
AUX4
AUX3
Vcc
Vss
AUX2
AUX1
AUX0
VPP
HA2
Vcc
Pin Name
Function
ES4408F Terminal Function
Pin No.
I/O
1 Vcc I 3.6V power supply
2 LA 4 O Device address output
3 LA 5 O Device address output
4 LA 6 O Device address output
5 LA 7 O Device address output
6 LA 8 O Device address output
7 LA 9 O Device address output
8 Vss I GND
9 Vcc I 3.6V power supply
10 LA 10 O Device address output
11 LA 11 O Device address output
12 LA 12 O Device address output
13 LA 13 O Device address output
14 LA 14 O Device address output
15 LA 15 O Device address output
16 LA 16 O Device address output
17 Vss I GND
18 Vcc I 3.6V power supply
19 LA 17 O Device address output
20 LA 18 O Device address output
21 LA 19 O Device address output
22 LA 20 O Device address output
23 LA 21 O Device address output
24 RESET# I Reset input, active low
25
TDMDX O TDM transmit data
RSEL I ROM select
26 Vss I GND
27 Vcc I 3.6V power supply
28 TDMDR I TDM receive data
ES4408F (DVD: IC101)
29 TDMCLK I TDM clock input
30 TDMFS I TDM frame sync
31 TDMTSC# O TDM output enable, active low
32
TWS O Audio transmit frame sync
SEL_PLL1 I Select PLL1
33
TSD0 O Audio transmit serial data port0
SEL_PLL0 I Select PLL0
34 Vss I GND
35 Vcc I 3.6V power supply
36 TSD1 O Audio transmit serial data port1
37 TSD2 O Audio transmit serial data port2
38 TSD3 O Audio transmit serial data port3
39 MCLK I/O Audio master clock for audio DAC
40 TBCK I/O Audio transmit bit clock
41
SPDIF_DOBM
O S/PDIF (IEC958) format output
42 NC No connect pin
43 Vss I GND
44 Vcc I 3.6V power supply
45 RSD I Audio receive serial data
46 RWS I Audio receive frame sync
47 RBCK I Audio receive bit clock
48 APLLCAP I Analog PLL capacitor
49 XIN I Crystal input
50 XOUT O Crystal output
51 Vcc I 3.6V power supply
52 Vss I GND
53 DMA 0 O DRAM address bus
54 DMA 1 O DRAM address bus
55 DMA 2 O DRAM address bus
Pin Name
FunctionPin No.
I/O