User's Manual

Turbo PMAC PCI HRM
2 Introduction
Option 4: CPU Type
The Turbo PMAC PC CPU piggyback board comes standard with a DSP56303 CPU IC as component
U1. This CPU has enough internal memory to process the servo and commutation for the first 15
motors. The algorithms for the last 17 motors must be processed from slower external memory. The
optional DSP56309 CPU has additional internal memory, so the processing of these motors is
significantly improved. The processor type in the board is reported on receipt of the CPU command.
• Option 4C: 80 MHz DSP56309 CPU IC. Recommended for control of more than 16 axes,
especially with PMAC-based commutation. Not compatible with Options 5Dx.
• Option 4D: 100 MHz DSP56309 CPU IC. Recommended for control of more than 16 axes,
especially with PMAC-based commutation. Not compatible with Options 5Cx (including the
default Option 5C0.
Option 5: CPU and Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes on the
piggyback CPU board. Only one Option 5xx may be selected for the board.
The CPU is a DSP5630x IC as component U1. It is currently available only as an 80 MHz device
(with computational power equivalent to a 120 MHz non-Turbo PMAC).
The compiled/assembled-program memory SRAM ICs are located in U14, U15, and U16. These ICs
form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms.
These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the
larger 512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory SRAM ICs are located in U11, U12, and U13. These ICs form the active
memory for user motion programs, uncompiled PLC programs, and user tables and buffers. These can
be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k
x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The flash memory IC is located in U10. This IC forms the non-volatile memory for the board’s
firmware, the user setup variables, and for user programs, tables, and buffers. It can be 1M x 8, 2M x
8, or 4M x 8 in capacity.
• Option 5C0 is the standard CPU and memory configuration. It is provided automatically if
Option 5xx is not specified. It provides an 80 MHz CPU (120 MHz PMAC equivalent), 128k
x24 of compiled/assembled program memory, 128k x 24 of user data memory; and a 1M x 8 flash
memory.
• Option 5C1 provides an 80 MHz CPU (120 MHz PMAC equivalent), 128k x 24 of
compiled/assembled program memory, an expanded 512k x 24 of user data memory, and a 2M x
8 flash memory.
• Option 5C2 provides an 80 MHz CPU (120 MHz PMAC equivalent), an expanded 512k x 24 of
compiled/assembled program memory, 128k x 24 of user data memory, and a 2M x 8 flash
memory.
• Option 5C3 provides an 80 MHz CPU (120 MHz PMAC equivalent), an expanded 512k x 24 of
compiled/assembled program memory, an expanded 512k x 24 of user data memory, and a 4M x
8 flash memory.
• Option 5D0 provides a 100 MHz CPU (150 MHz PMAC equivalent), 128k x24 of
compiled/assembled program memory, 128k x 24 of user data memory; and a 1M x 8 flash
memory.
• Option 5D1 provides a 100 MHz CPU (150 MHz PMAC equivalent), 128k x 24 of
compiled/assembled program memory, an expanded 512k x 24 of user data memory, and a 2M x
8 flash memory.