User's Manual

PMAC2 User Manual
Using the PMAC2 to Interrupt the Host Computer 91
USING THE PMAC2 TO INTERRUPT THE HOST COMPUTER
Programmable Interrupt Controller (PIC)
The PC versions of the PMAC2 have a built-in programmable interrupt controller (PIC) that can be used
to let PMAC2 interrupt the host computer over the PC bus. Any of eight signals on PMAC2 can be used
for these interrupts. The PIC is similar, but not identical, to the 8259 PIC on the PMAC1 and in the PC.
Interrupt Controller Structure
The PIC appears as four 8-bit registers in the I/O space of the PC. The actual address of these registers
depends on the setting of the base address (Base) of the PMAC2 in the I/O space of the PC as set by the
Dip switches on SW1. These four registers are:
• Base+8: Interrupt Status Register
• Base+9: Interrupt Signal Status Register
• Base+10: Interrupt Mask Control Register
• Base+11: Interrupt Edge/Level Control Register
With the base address at the factory default of 528 (210 hex), these four registers are at 536-539 (218-21B
hex).
The eight bits in each register represent the status or control of the eight interrupt source signals as
follows:
• Bit 0: IPOS: In-position for the addressed coordinate system
• Bit 1: BREQ: Buffer-request for the addressed coordinate system
• Bit 2: EROR: Fatal following error for the addressed coordinate system
• Bit 3: F1ER: Warning following error for the addressed coordinate system
• Bit 4: HREQ: Host-request
• Bit 5: EQU1: Position Compare 1 (PMAC2 PC and PMAC2 Lite only)
(also used for DPRAM ASCII interrupt)
• Bit 6: EQU5: Position Compare 5 (PMAC2 PC only)
EQU2: Position Compare 2 (PMAC2 Lite only)
• Bit 7: WD0: Watchdog Timer
A jumper is used to select which PC interrupt line receives the interrupt signal from PMAC2. The
choices are:
• E7: IRQ10
• E8: IRQ11
• E9: IRQ12
• E10: IRQ14
• E11: IRQ15 (on newer
PIC Registers
Interrupt Status Register (Base+8)
This register, when read, shows the status of the eight interrupts. It will be read by any interrupt service
routine to find out which signal created the interrupt to the PC. A 1 in a bit indicates an interrupt for the
matching signal; a 0 indicates no interrupt. An interrupt signal must be unmasked before it can show an
interrupt in this register. The act of writing to this register will clear any edge-triggered interrupts, no
matter what value is written.
Interrupt Signal Status Register (Base+9)
This register, when read, shows the status of the eight signal inputs to the PIC. It is not useful in interrupt
service routines, but provides a fast and easy method for polling the status of these signals without any
overhead to the PMAC2.