User's Manual

PMAC2 User Manual
PMAC2 General Purpose I/O Use 81
Multiplexer Port (JTHW)
The JTHW multiplexer port has 16 discrete digital I/O lines for general purpose use. The lines are
configurable by byte for input or output (on the DSPGATE2 I/O IC, the lines are individually
configurable for input or output, but the buffer ICs are only byte-configurable), and individually
configurable for inverting or non-inverting format.
Hardware Characteristics
When configured as an output, each line has a 5V CMOS totem-pole driver. This driver can sink or
source up to 20 mA. There is a 10 kΩ pull-up resistor to 5V on each line for input purposes, but the
driver IC can hold the line high or low despite this resistor. When configured as an input, the buffer IC
presents a high-impedance input either sinking or sourcing; no significant current will flow. The pull-up
resistor on the line will bias the line high in the absence of anything actively pulling the line low at
significantly lower impedance.
Suggested M-Variables
The 16 I/O lines are memory-mapped into PMAC's address space in register Y:$C082. Typically, these
lines are used as a unit with specially designed multiplexing I/O accessories and appropriate multiplexing
M-variables (TWB, TWD, TWR, and TWS formats), in which case PMAC2 handles the direct control of
these I/O lines automatically. However, these lines can also be accessed individually with M-variables.
Following is a suggested set of M-variable definitions to use these data lines:
M40->Y:$C082,8 ; SEL0 Line; J2 Pin 4
M41->Y:$C082,9 ; SEL1 Line; J2 Pin 6
M42->Y:$C082,10 ; SEL2 Line; J2 Pin 8
M43->Y:$C082,11 ; SEL3 Line; J2 Pin 10
M44->Y:$C082,12 ; SEL4 Line; J2 Pin 12
M45->Y:$C082,13 ; SEL5 Line; J2 Pin 14
M46->Y:$C082,14 ; SEL6 Line; J2 Pin 16
M47->Y:$C082,15 ; SEL7 Line; J2 Pin 18
M48->Y:$C082,8,8,U ; SEL0-7 Lines treated as a byte
M50->Y:$C082,0 ; DAT0 Line; J2 Pin 3
M51->Y:$C082,1 ; DAT1 Line; J2 Pin 5
M52->Y:$C082,2 ; DAT2 Line; J2 Pin 7
M53->Y:$C082,3 ; DAT3 Line; J2 Pin 9
M54->Y:$C082,4 ; DAT4 Line; J2 Pin 11
M55->Y:$C082,5 ; DAT5 Line; J2 Pin 13
M56->Y:$C082,6 ; DAT6 Line; J2 Pin 15
M57->Y:$C082,7 ; DAT7 Line; J2 Pin 17
M58->Y:$C082,0,8,U ; DAT0-7 Lines treated as a byte
Direction Control
In the default configuration automatically set at power-up/reset, DAT0 to DAT7 are set up as non-
inverting inputs; SEL0 to SEL7 are set up as non-inverting outputs with a zero (low voltage) value. If
any of the multiplexer port accessories are to be used, this configuration must not be changed.
The direction control bit for each of these I/O bits is in the corresponding bit in the matching X register.
For example, the direction control bit for DAT3 is located at X:$C082,3; the direction control bit for
SEL6 is located at X:$C082,14. Because the buffer ICs can only be switched by byte, it is best to define
8-bit M-variables for the direction control. Suggested definitions are:
M60->X:$C082,0,8 ; Direction control for DAT0 to DAT7
M62->X:$C082,8,8 ; Direction control for SEL0 to SEL7
These M-variables should take values of 0 or 255 ($FF) only; 0 sets the byte to input, 255 sets the byte to
output.