User's Manual

PMAC2 User Manual
Setting Up PMAC2 for Pulse-and-Direction Control 59
The PFMCLK/addition frequency sets a lower limit on the pulse frequency as well – an absolute limit of
one eight-millionth of the addition frequency (without dithering). The default frequency of approximately
10 MHz can provide a useful range of about 1 Hz to 1 million Hz, and is suitable for a wide variety of
applications, especially with microstepping drives. For full or half step drives, the PFMCLK/addition
frequency will probably be set considerably lower – to the approximately 1.2 MHz or 600 kHz settings.
I903 controls the PFMCLK frequency for axis interface channels 1 to 4; I907 does the same for axis
interface channels 5 to 8; I993 does the same for supplementary channel 1*. The input to the clock
control circuitry is a 39.3216 MHz signal; this can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 to create the
PFMCLK signal. Therefore, the possible PFMCLK frequencies are:
Divide By: Divider N (1/2^N) PFMCLK Freq
1 0 39.3216 MHz
2 1 19.6608 MHz
4 2 9.8304 MHz
8 3 4.9152 MHz
16 4 2.4576 MHz
32 5 1.2288 MHz
64 6 611.44 kHz
128 7 305.72 kHz
The divider N is used in these I-variable to determine the frequency.
These variables also independently control the frequencies of the encoder sample clock SCLK, plus the
clocks for the serial D/A and A/D converters, DACCLK and ADCCLK. They are also divided down in
the same way from the same 39.3216 MHz signal. The SCLK frequency should be the same as the
PFMCLK frequency if the pulse train is fed into the encoder counters.
PFM Pulse Width: I904, I908, I994
I904 controls the pulse width for axis interfaces 1 to 4; I908 does the same for axis interfaces 5 to 8; and
I994 does so for supplementary channel 1*. The pulse width is specified in PFMCLK cycles; the range is
1 to 255 cycles.
The minimum gap between pulses is equal to the pulse width, so the minimum pulse cycle period is twice
the pulse width set here. This sets a maximum frequency of the PFM output. If the algorithm asks for a
higher frequency, PMAC2 will not produce the requested frequency.
Parameters to Set Up Per-Channel Hardware Signals
For the circuitry of each of the 8 machine interface channels, there are several hardware setup I-variables,
arranged in sets of 10. I910 to I919 control the circuitry for machine interface channel 1 (usually used
with motor 1); I920 to I929 control for machine interface channel 2, and so on. An 'n' in place of the ten's
digit permits us to talk generically about a variable for interface channel n; for example I9n6 refers to
I916 for machine interface channel 1, and to I976 for machine interface channel 7.
Output Mode Control: I9n6
I9n6 controls what types of signals are brought out from Channel n’s A, B, and C command registers; it
must be set to 2 or 3 to use the PFM signals from the C register.
Output Inversion Control: I9n7
I9n7 controls whether the pulse signals are inverted or not. A value of 0 or 1 means the C pulse is high-
true; a value of 2 or 3 means that it is low true.
PFM Direction Inversion Control: I9n8
I9n8 controls the polarity of the PFM direction signal. A value of 0 means positive direction is low; a
value of 1 means the negative direction is low.