User's Manual

PMAC2 User Manual
58 Setting Up PMAC2 for Pulse-and-Direction Control
Signal Timing
The PULSEn and DIRn signals are driven from the internal PFM_CLK signal, whose frequency is
controlled by I903 or I907 (see below). The width of the pulse is controlled by the PFM_CLK frequency
and I904 or I908 (see below). The output on PULSEn can be high-true (high during pulse, low
otherwise) or low-true, as controlled by I9n7; the default is high-true. The polarity of the DIRn is
controlled by I9n8.
PULSEn and DIRn signals can only change on the rising edge of PFM_CLK. If DIRn changes on a
pulse, it will change simultaneously with the front end of PULSEn. Some stepper drives require a setup
time on the DIRn line before the rising edge of PULSEn; these systems can be accommodated by
inverting the PULSEn signal with I9n7.
The DIRn signal is latched in this state at least until the front end of the next pulse. The PULSEn signal
stays true for the number of PFM_CLK cycles set by I904 or I908. It then goes false and stays false for a
minimum of this same time. This guarantees that the pulse duty cycle never exceeds 50%; the pulse
signal can be inverted with I9n7 without violating minimum pulse width specifications.
Note:
Some older stepper drives sample the DIRn line in software and assume that all of
the pulses received since the last software sample are in that direction. This
requires a long direction setup time than the PMAC2 can directly produce. In
these cases, simple logic external to PMAC2 may be required to swallow the first
pulse produced after a direction change.
Furthermore, it is the modified pulse train out of the pulse swallower that must be fed into the PMAC2
encoder counter to simulate a closed loop. Therefore, these systems must have some sort of loop-back
circuitry, usually on the same board as the pulse swallower, and must use an I9n0 decode setting to accept
external pulse and direction (=0 or 4) rather than internal pulse and direction (=8). Delta Tau's Acc-8S
stepper interface board contains this pulse swallowing circuitry; I9n0 should be set to 0 for any channel
using the Acc-8S.
Parameter Setup
Several PMAC2 I-variables must be set correctly to generate and use the PFM circuitry properly. This
section covers each of these variables. (Note: The PMAC2 I-variables that control the hardware setup of
the DSP-GATE ASIC – those in the I900s – are in general different in meaning from those for the
original PMAC, because of the difference in the ASICs.).
Parameters to Set Up Global Hardware Signals
PFM Clock Frequency Control: I903, I907, I993
An I-variable controls the frequency of addition of the command value into the accumulator by setting the
frequency of a clock signal called PFMCLK. One addition is performed during each PFMCLK cycle, so
the addition frequency is equal to the PFMCLK frequency. The pulse frequency for a given command
value is directly proportional to this addition frequency.
This PFMCLK/addition frequency puts an upper limit on the pulse frequency that can be generated --
with an absolute limit of 1/4 of the PFMCLK/addition frequency. Depending on the worst-case
frequency distortion that can be tolerated at high speeds, most people will limit their maximum pulse
frequency to 1/10 of the PFMCLK/addition frequency. Therefore, they will select a PFMCLK/ addition
frequency 10 to 20 times greater than their maximum desired pulse frequency.