User's Manual
PMAC2 User Manual
54 Setting Up PMAC2 For Velocity or Torque Control
The servo clock frequency is determined by the settings of I900, I901, and I902.
I900 determines the frequency of the MaxPhase clock signal from which the actual phase clock and servo
clock signals are derived. It also determines the PWM cycle frequency for Channels 1 to 4. To generate
any PWM signals on Channels 1-4, refer to the Using PMAC2 for Direct PWM Control section for details
and use I901 to select how the PHASE clock is derived from MaxPhase.
If PWM signals do not need to be generated on channels 1-4, set I900 to make the MaxPhase clock
frequency equal to the PHASE clock frequency wanted. This must be an integer multiple of the SERVO
clock frequency wanted. Use the following formula:
I
kHz
MaxPhaseFreq kHz
900
117 8
2
1=−
int
,964.
*()
I901 determines how the actual phase clock is generated from the MaxPhase clock, using the equation:
1901
I
)kHz(eqMaxPhaseFr
)kHz(PhaseFreq
+
=
I901 is an integer value with a range of 0 to 15, permitting a division range of 1 to 16. If the MaxPhase
frequency is set equal to the desired phase clock frequency, make I901 equal to 0 for the divide-by-1
setting.
I902 determines how the Servo clock is generated from the Phase clock, using the equation
1902I
)kHz(PhaseFreq
)kHz(ServoFreq
+
=
I902 is an integer value with a range of 0 to 15, permitting a division range of 1 to 16.
I10 tells the PMAC2 interpolation routines how much time there is between servo clock cycles. It must
be changed any time I900, I901, or I902 is changed. I10 can be set according to the formula:
()()()
1902I1901I3900I*2
9
640
10I +++=
Hardware Clock Frequency Control: I903, I907
I903 determines the frequency of four hardware clock signals use for machine interface channels 1-4;
I907 does the same for machine interface channels 5-8. These can probably be left at the default values.
The four hardware clock signals are SCLK (encoder sample clock), PFM_CLK (pulse frequency
modulator clock, DAC_CLK (digital-to-analog converter clock), and ADC_CLK (analog-to-digital
converter clock).
Only the DAC_CLK signal is directly used with the analog output, to control the frequency of the serial
data stream to the DACs. The default DAC clock frequency of 4.9152 MHz is suitable for the DACs on
the recommended Acc-8E analog interface board. Refer to the I903 and I908 descriptions for detailed
information on setting these variables.
The encoder SCLK frequency should be at least 20% greater than the maximum count (edge) rate that is
possible for the encoder on any axis. Higher SCLK frequencies than this minimum may be used, but
these make the digital delay anti-noise filter less effective.
DAC Strobe Control: I905, I909
PMAC2 generates a common DAC strobe word for each set of four machine interface channels. It does
this by shifting out a 24-bit word each phase cycle, one bit per DAC clock cycle, most significant bit first.
I905 contains this word for Channels 1-4; I909 contains this word for Channels 5-8. The default values of
$7FFFC0 are suitable for use with the DACs on the recommended Acc-8E analog interface board.